NAND Gate Universal Logic Circuit Simulator

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Was du lernst

Read the NAND truth table — output 1 unless every input is 1.
Recognise NAND as functionally complete: every Boolean function can be built from NANDs.
Construct NOT, AND, OR, XOR from NAND gates alone.
Identify NAND in CMOS: 4 transistors arranged 2-series + 2-parallel.
Spot NAND-based SR latches as the seed of all sequential logic.

So funktioniert es

NAND is AND followed by NOT: Y = ¬(A · B). Output is 1 unless every input is 1, in which case it drops to 0. The truth table is exactly inverted from AND — only the all-ones row outputs 0.

NAND's superpower is functional completeness: any Boolean function can be built from NAND gates alone. Specifically: - NOT(A) = NAND(A, A) — feed both inputs the same signal, NAND becomes inversion. - AND(A, B) = NOT(NAND(A, B)) = NAND(NAND(A, B), NAND(A, B)). - OR(A, B) = NAND(NOT A, NOT B) = NAND(NAND(A, A), NAND(B, B)). - XOR(A, B) = NAND(NAND(A, NAND(A, B)), NAND(B, NAND(A, B))).

Why does this matter? Because any logic family that includes NAND is automatically capable of expressing every possible Boolean function. Most CMOS standard-cell libraries make NAND (and NOR) their fastest, smallest gates because of this.

In silicon, NAND is structurally elegant: two NMOS transistors in series (between output and ground) and two PMOS transistors in parallel (between output and Vdd). The series-parallel symmetry gives clean, fast switching with only 4 transistors.

This circuit demonstrates a basic 2-input NAND directly, plus its derived NOT (NAND with tied inputs).

Wahrheitstabelle

NAND has 4 input rows. Output is 0 only on the all-ones row — the inverse of AND.

Eingänge		Ausgang
A	B	Y
0	0	1	Default high — neither input asserts
0	1	1
1	0	1
1	1	0	Both 1 — output drops to 0 (the only NAND-low row)

Boolescher Ausdruck

Y = \overline{A \cdot B}

NAND: NOT(AND(A, B)). Output high unless every input is 1.

\overline{A} = \text{NAND}(A, A)

Tying both NAND inputs together produces an inverter — proof of NAND universality (NOT).

A \cdot B = \overline{\text{NAND}(A, B)}

Inverting NAND recovers AND.

A + B = \text{NAND}(\overline{A}, \overline{B})

OR via De Morgan: invert both inputs, NAND them. Three NANDs total (two as inverters, one for the NAND of inverses).

Schritt für Schritt ausprobieren

Stelle die Eingänge in der Einbettung oben ein, lies was passieren sollte und überprüfe es.

1

A = 0 B = 0

Erwartet: Y = 1

Was du siehst: Both off — NAND defaults high. Notice this is the opposite of AND, where the same inputs produce 0.
2

A = 1 B = 0

Erwartet: Y = 1

Was du siehst: One input high, one low — NAND stays high. Need both inputs high to make NAND drop.
3

A = 0 B = 1

Erwartet: Y = 1

Was du siehst: Symmetric — order doesn't matter for NAND (it's commutative).
4

A = 1 B = 1

Erwartet: Y = 0

Was du siehst: Both inputs high — NAND drops to 0. This is the only row where it's low. The opposite of AND.

Verwendete Komponenten

Praxisanwendungen

Standard-cell libraries. Production ASIC and FPGA flows use NAND2 as a fundamental cell. Synthesis tools translate any logic into a NAND-rich netlist because NANDs are the fastest, smallest gates in CMOS.

Memory cells (SRAM cross-couples). A 6-transistor SRAM cell is two cross-coupled inverters with access transistors — and an inverter is just NAND with tied inputs. The bistable storage is implicit NAND-NAND feedback.

SR-latch cores. Cross-coupled NAND latches (active-low set/reset) are the basis of all sequential logic. Every flip-flop in a CPU started life as a NAND-NAND latch.

Schmitt-trigger inputs. Some I/O buffers use a NAND-based Schmitt trigger to clean up noisy signals — the hysteresis prevents oscillation around the threshold.

Logic synthesis benchmarks. Academic research on logic minimisation often counts "literal cost" or "NAND count" as a complexity metric — fewer NANDs = simpler implementation.

Häufig gestellte Fragen

Why is NAND called the 'universal' gate?

Because every Boolean function can be expressed using only NAND gates. NOT is NAND(A,A); AND is NAND followed by another NAND-as-inverter; OR is NAND of inverted inputs. With NAND alone you have a complete logic family — no need for any other gate type.

Is NOR also universal?

Yes — NOR is the dual of NAND. NOR(A,A) = NOT(A); NOR(NOR(A,A), NOR(B,B)) = AND(A,B); etc. CMOS designers sometimes prefer NAND because NMOS series stacks (NAND's structure) are faster than PMOS series stacks (NOR's structure).

How many NAND gates does it take to build XOR?

Four NAND2 gates is the minimum: NAND of A and B is shared; that result NANDs with A and with B separately; the final NAND combines those two. The result is XOR.

What about NAND with more than 2 inputs?

Wide NANDs exist (NAND3, NAND4) but their speed degrades with width because the series NMOS stack grows. Most production cells stop at NAND4; wider NANDs are typically built from NAND2/NAND3 trees.

Why is NAND faster than NOR in most CMOS processes?

In CMOS, NMOS transistors switch ~2× faster than PMOS for equal size. NAND has NMOS in series and PMOS in parallel — the slow part (PMOS) is parallel (fast). NOR has it reversed — PMOS series is the slow stack. Hence NAND wins on speed.