NAND Gate Universal Logic
NAND gate demonstration showing its universal property. Learn how NAND can implement other logic functions. Essential for understanding digital design.
您将学到什么
- Read the NAND truth table — output 1 unless every input is 1.
- Recognise NAND as functionally complete: every Boolean function can be built from NANDs.
- Construct NOT, AND, OR, XOR from NAND gates alone.
- Identify NAND in CMOS: 4 transistors arranged 2-series + 2-parallel.
- Spot NAND-based SR latches as the seed of all sequential logic.
工作原理
NAND is AND followed by NOT: Y = ¬(A · B). Output is 1 unless every input is 1, in which case it drops to 0. The truth table is exactly inverted from AND — only the all-ones row outputs 0.
NAND's superpower is functional completeness: any Boolean function can be built from NAND gates alone. Specifically: - NOT(A) = NAND(A, A) — feed both inputs the same signal, NAND becomes inversion. - AND(A, B) = NOT(NAND(A, B)) = NAND(NAND(A, B), NAND(A, B)). - OR(A, B) = NAND(NOT A, NOT B) = NAND(NAND(A, A), NAND(B, B)). - XOR(A, B) = NAND(NAND(A, NAND(A, B)), NAND(B, NAND(A, B))).
Why does this matter? Because any logic family that includes NAND is automatically capable of expressing every possible Boolean function. Most CMOS standard-cell libraries make NAND (and NOR) their fastest, smallest gates because of this.
In silicon, NAND is structurally elegant: two NMOS transistors in series (between output and ground) and two PMOS transistors in parallel (between output and Vdd). The series-parallel symmetry gives clean, fast switching with only 4 transistors.
This circuit demonstrates a basic 2-input NAND directly, plus its derived NOT (NAND with tied inputs).
真值表
NAND has 4 input rows. Output is 0 only on the all-ones row — the inverse of AND.
| 输入 | 输出 | ||
|---|---|---|---|
| A | B | Y | |
| 0 | 0 | 1 | Default high — neither input asserts |
| 0 | 1 | 1 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 | Both 1 — output drops to 0 (the only NAND-low row) |
布尔表达式
NAND: NOT(AND(A, B)). Output high unless every input is 1.
Tying both NAND inputs together produces an inverter — proof of NAND universality (NOT).
Inverting NAND recovers AND.
OR via De Morgan: invert both inputs, NAND them. Three NANDs total (two as inverters, one for the NAND of inverses).
逐步尝试
在上方嵌入式电路中设置输入，然后阅读预期结果并验证。
- 1A = 0 B = 0预期:
Y = 1您将看到: Both off — NAND defaults high. Notice this is the opposite of AND, where the same inputs produce 0. - 2A = 1 B = 0预期:
Y = 1您将看到: One input high, one low — NAND stays high. Need both inputs high to make NAND drop. - 3A = 0 B = 1预期:
Y = 1您将看到: Symmetric — order doesn't matter for NAND (it's commutative). - 4A = 1 B = 1预期:
Y = 0您将看到: Both inputs high — NAND drops to 0. This is the only row where it's low. The opposite of AND.
使用的组件
实际应用
Standard-cell libraries. Production ASIC and FPGA flows use NAND2 as a fundamental cell. Synthesis tools translate any logic into a NAND-rich netlist because NANDs are the fastest, smallest gates in CMOS.
Memory cells (SRAM cross-couples). A 6-transistor SRAM cell is two cross-coupled inverters with access transistors — and an inverter is just NAND with tied inputs. The bistable storage is implicit NAND-NAND feedback.
SR-latch cores. Cross-coupled NAND latches (active-low set/reset) are the basis of all sequential logic. Every flip-flop in a CPU started life as a NAND-NAND latch.
Schmitt-trigger inputs. Some I/O buffers use a NAND-based Schmitt trigger to clean up noisy signals — the hysteresis prevents oscillation around the threshold.
Logic synthesis benchmarks. Academic research on logic minimisation often counts "literal cost" or "NAND count" as a complexity metric — fewer NANDs = simpler implementation.