JK Flip-Flop Master-Slave
JK flip-flop with all input combinations and oscilloscope. Advanced flip-flop operation without race conditions.
배울 내용
- Recognize the four JK input modes: hold, reset, set, toggle.
- Use J=K=1 as a toggle command — the key advantage over SR.
- Understand master-slave construction and how it solves the race-around problem.
- Build a divide-by-2 frequency divider using JK in toggle mode.
- Distinguish JK from D flip-flops and pick the right one per use case.
작동 원리
A JK flip-flop generalizes the SR flip-flop by reinterpreting the forbidden state (S=R=1) as a toggle command (J=K=1 means flip Q to its complement). It's edge-triggered, typically built from a master-slave pair of latches.
Behaviour at the rising clock edge: - J=0, K=0: Hold (Q stays the same). - J=0, K=1: Reset (Q = 0). - J=1, K=0: Set (Q = 1). - J=1, K=1: Toggle (Q = ¬Q — flips on every clock edge).
The toggle behaviour makes JK flip-flops useful for counters: tying both J and K to 1 makes the FF flip on every clock, dividing the clock frequency by 2. Cascading several JK flip-flops in toggle mode produces a binary counter — exactly the pattern used in ripple counters.
Master-slave construction: two cross-coupled latches in series with opposite clock phases. The master responds while clock is low; the slave passes the master's value through while clock is high. The crucial race-around problem of the JK in toggle mode (where Q would oscillate during clock-high if it could) is solved by master-slave timing: only the rising edge propagates a single Q transition.
JK flip-flops are less common in modern designs (D flip-flops with an XOR gate on D give equivalent behaviour with fewer transistors), but they're a standard textbook topic and appear in some standard cell libraries.
진리표
JK behaviour at the rising clock edge. Toggle (J=K=1) is the unique JK feature.
| 입력 | 출력 | ||
|---|---|---|---|
| J | K | Q (next) | |
| 0 | 0 | 0 | Hold — Q unchanged |
| 0 | 1 | 0 | Reset — Q = 0 |
| 1 | 0 | 1 | Set — Q = 1 |
| 1 | 1 | 1 | Toggle — Q flips (here from 0 to 1) |
불 대수식
Characteristic equation: J sets a 0 to 1; K resets a 1 to 0. The four combinations cover all behaviours.
단계별로 시도해 보세요
위 임베드에서 입력을 설정한 후, 예상 결과를 읽고 직접 확인하세요.
- 1J = 0 K = 0 CLK = rising예상:
Q unchanged관찰 포인트: Hold mode — clock edge does nothing. Q stays at its current value. - 2J = 1 K = 0 CLK = rising예상:
Q = 1관찰 포인트: Set mode — Q goes to 1 on the edge. Clock edge required (no async behaviour). - 3J = 0 K = 1 CLK = rising예상:
Q = 0관찰 포인트: Reset mode — Q goes to 0. Same edge-triggered timing as Set. - 4J = 1 K = 1 CLK = running예상:
Q toggles every clock edge관찰 포인트: Toggle mode — Q flips back and forth on each rising edge. Watch the output light blink at half the clock frequency. This is the divide-by-2 behavior used in ripple counters.
사용된 구성 요소
실제 응용 사례
Binary counter cells. A JK flip-flop with J=K=1 toggles on every clock edge — exactly a divide-by-2 stage. Cascading N of them produces an N-bit ripple counter.
T flip-flop construction. A T flip-flop is a JK with J and K tied together. JK is more general; T is the specialization for toggle-only behaviour.
Mode-controlled state machines. When the FSM needs distinct set/reset/toggle/hold transitions per state, JK's 4 modes match neatly without external multiplexing.
Educational stepping stone. JK flip-flops bridge SR latches (forbidden state) and D flip-flops (single data input) by repurposing the forbidden state into the useful toggle behaviour.
Asynchronous frequency dividers. Older clock-divider circuits used JK in toggle mode for simple divide-by-2N chains — straightforward, low transistor count.