D Flip-Flop Edge-Triggered Circuit Simulator

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JavaScript を有効にするとライブ回路が読み込まれます。下の真理値表で動作を確認できます。

学べること

Distinguish edge-triggered (D flip-flop) from level-sensitive (D latch) behaviour.
Understand setup, hold, and clock-to-Q propagation timing.
Recognise the master-slave latch construction inside a D flip-flop.
See why flip-flops are glitch-immune compared to latches.
Connect D flip-flops to register files, pipeline stages, and FSMs.

仕組み

A D flip-flop is the workhorse of synchronous digital design. Unlike a latch (level-sensitive), a flip-flop is edge-triggered: Q captures D only at the moment of a clock edge (rising or falling, depending on type). Between edges, D can change freely without affecting Q.

Internal construction: master-slave configuration of two D latches with opposite clock phases. The master latch is transparent when CLK = 0 (capturing D's current value); the slave is transparent when CLK = 1 (releasing the captured value to Q). The transition CLK 0→1 is the rising edge that propagates the master's last value to the output. After the edge, the master closes again — D changes don't reach Q until the next rising edge.

Key timing parameters: - Setup time: D must be stable for some time *before* the clock edge. - Hold time: D must remain stable for some time *after* the clock edge. - Propagation delay (CLK-to-Q): Time from clock edge to Q changing.

Flip-flops are glitch-immune: D can wiggle as much as it wants between edges, but only the value at the edge matters. This makes synchronous design dramatically easier than purely latch-based design.

Every register, every pipeline stage, every state machine flip-flop in modern CPUs uses edge-triggered D flip-flops as its core storage primitive.

真理値表

D flip-flop with rising-edge trigger. ↑ denotes the clock rising edge.

入力		出力
CLK	D	Q
0	0	0	Clock low — Q holds (D ignored)
0	1	0	Clock low — Q still holds
1	0	0	Clock high after edge — Q = D from edge time
1	1	1	Clock high after edge — Q = D from edge time

ブール式

Q_{n+1} = D \quad \text{at } \uparrow \text{CLK}

On the rising clock edge, Q captures D. Between edges, Q holds.

Q_{n+1} = Q_n \quad \text{otherwise}

Holding behaviour: Q doesn't change unless an active clock edge arrives.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

CLK = running D = 0 then 1 between edges

期待値: Q changes only at the next rising edge

観察ポイント: Toggle D rapidly between clock edges — Q ignores the changes. Only the value of D at the rising edge matters.
2

CLK = stopped low D = 0 → 1 → 0

期待値: Q frozen

観察ポイント: Stop the clock — Q can't change at all, regardless of D. Flip-flops require a clock edge to update.
3

CLK = single rising edge D = 1 at edge

期待値: Q = 1 after the edge

観察ポイント: A single clock pulse with D=1 captures D into Q. Q stays at 1 until the next rising edge.
4

CLK = running D = static 0

期待値: Q = 0 every clock

観察ポイント: Constant D — every clock edge captures the same value. Q stays steady at D's value.

使用コンポーネント

実世界での応用

CPU register files. Each register is N D flip-flops in parallel, all clocked by the system clock. The CPU writes a register by raising its write-enable on a clock edge.

Pipeline stages. A 5-stage CPU pipeline has 4 sets of flip-flops between consecutive stages. Each clock edge advances data one stage forward.

Synchronous state machines. FSM state registers use D flip-flops; on each clock edge, the next-state combinational logic's output replaces the current state.

Bus interface registers. External buses are sampled into registers via flip-flops to synchronize foreign data into the CPU clock domain.

FIFO buffers. Each FIFO entry is a row of D flip-flops with controlled write-enable and read-pointer logic.

よくある質問

Why is the D flip-flop edge-triggered instead of level-sensitive?

Glitch immunity. D can wiggle freely between clock edges without affecting Q. Synchronous designs rely on this — combinational outputs settle, and the next clock edge captures the final stable value.

What's setup time?

The minimum stable time D must precede the active clock edge. Below this, the flip-flop may enter metastability or capture an indeterminate value. Typical CMOS setup times are 50–300 ps.

What's hold time?

The minimum stable time D must remain after the active clock edge. Below this, the flip-flop may not correctly latch the pre-edge value. Hold times are typically much shorter than setup — often near zero in modern processes.

What's the master-slave latch chain?

Two D latches in series. The master is transparent when clock is low; the slave is transparent when clock is high. The clock edge propagates the master's stable value to the slave (and to Q). This construction gives flip-flops their edge-triggered behaviour.

How is rising-edge vs. falling-edge triggering chosen?

Either works — most cell libraries provide both flavours. Rising-edge is more common in textbooks; falling-edge is sometimes used to simplify clock-tree design where the active phase is the first half-cycle. The behavioural model is identical, just inverted clock polarity.