Complex Logic Circuit Demo Simulator

学べること

仕組み

真理値表

ブール式

順を追って試す

使用コンポーネント

実世界での応用

よくある質問

インタラクティブシミュレーターには JavaScript が必要です

JavaScript を有効にするとライブ回路が読み込まれます。下の真理値表で動作を確認できます。

Trace signals through multi-stage combinational circuits.
Convert a gate-level circuit into its Boolean expression.
Build the truth table for a 4-input combinational network.
Recognise that multi-level Boolean networks can be simpler than 2-level SOPs.
Apply Karnaugh maps to simplify the resulting expressions.

This circuit demonstrates composition of multiple combinational stages — chains of AND, OR, NOT, XOR gates working together to compute a more elaborate Boolean function. Each gate's output feeds the next stage, building a multi-level network.

Reading the circuit: 1. Start at the inputs and trace each signal through every gate it touches. 2. Write down the intermediate signal at each gate's output as a Boolean expression in the inputs. 3. The final output is the topmost expression — typically a sum-of-products or a more complex hierarchy.

For a circuit with 4 inputs, the truth table has 2⁴ = 16 rows. Filling in each row by tracing through the gates is the mechanical way to verify behaviour. Boolean simplification (Karnaugh maps, algebraic manipulation, or synthesis tools) shows whether the multi-stage circuit could be flattened into a smaller equivalent.

This kind of multi-stage composition is the bread-and-butter of combinational design: every Boolean function can be expressed as a 2-level SOP (sum of products) network, but multi-level networks are usually smaller, just slower (more gate delays).

Multi-stage circuits' truth tables follow from systematic gate-by-gate evaluation. Showing representative rows.

Y_1 = (A \cdot B) + (C \oplus D)

Sum of two product/XOR terms — multi-level expression with mixed gates.

Y_2 = \overline{(A + B)} \cdot (C \cdot D)

AND of inverted-OR with another AND — three levels of logic.

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

A = 0 B = 0 C = 0 D = 0

期待値: Y1=0, Y2=0

観察ポイント: All inputs low — neither output fires. Default state.
2

A = 1 B = 1 C = 0 D = 0

期待値: Y1=1, Y2=0

観察ポイント: AB term wins — Y1 fires. The other half (C and D) is dormant.
3

A = 0 B = 0 C = 1 D = 1

期待値: Y1=0, Y2=1

観察ポイント: CD term wins on Y2; the XOR(C,D) is 0 (both high) so Y1 stays low.
4

A = 1 B = 1 C = 1 D = 1

期待値: Y1=1, Y2=0

観察ポイント: Both halves active. Y1 fires (AB true). Y2 doesn't fire because A+B is true → its inverted-OR is false → AND is false.

ALU control logic. Decoding the operation field of an instruction into per-stage enables for adder, shifter, and logic units uses multi-stage Boolean networks.

Address decoders with enables. Multi-level decoders combine address bits, chip-select inputs, and bus-master enables to produce per-bank write strobes.

Permission and access logic. "Permit if (admin AND not-during-lockout) OR (owner AND read-only)" compiles into multi-stage Boolean networks.

Fault aggregation. "Critical fault if any of these specific subsets are tripped" — sums of products of fault flags.

Configuration logic. Hardware that selects between multiple modes based on configuration bits often has 4–6 input multi-level decision logic.

All inputs low — outputs default

AB term fires Y1

CD term fires Y2

Both halves active — both outputs high

How do I read the Boolean expression from the schematic?

Start at each input and label the wire with its signal name. At each gate, write the gate's expression in terms of its labeled inputs, then label the output wire. Continue until you reach the final output. The last expression is the function the circuit computes.

Can multi-stage logic always be flattened to 2-level SOP?

Yes — every Boolean function can be expressed as a 2-level SOP (or POS). But the flattened version may need many more gates. Multi-stage logic trades depth for area; SOP trades area for depth (faster but bigger).

How do Karnaugh maps help here?

K-maps give you the minimal SOP form for any function up to 4–6 variables. They group adjacent 1-cells into product terms. The minimal SOP can then be compared with the multi-stage circuit's gate count to decide which is preferable.

What's the longest path through this circuit?

Look for the longest chain of dependent gates from input to output. In a 3-stage circuit, that's typically 3 gate delays. Modern static-timing-analysis tools find this critical path automatically.

Is this how production combinational logic is designed?

Production designs use HDL (Verilog, VHDL) and synthesis tools that automatically generate multi-stage gate networks from high-level behaviour. The principles are the same — Boolean functions, multi-stage trade-offs — but humans rarely draw schematics by hand at scale.