Clock-Driven Crossing Lights Circuit Simulator

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您将学到什么

Drive a sequential pattern with a clock signal.
Use a toggle flip-flop to alternate between two states.
Connect Q and ¬Q outputs to drive complementary output lights.
Recognize that the output frequency is half the clock frequency.
Understand the simplest pattern of synchronous sequential logic.

工作原理

A clock-driven crossing lights circuit demonstrates how a clock signal can drive a simple alternating output sequence. The classic application: railroad crossing lights that alternate between two LEDs while a train approaches.

The core mechanism is a clock + flip-flop in toggle mode: each clock edge flips a stored bit, and the bit (and its complement) drive two output lights. Result: lights alternate at half the clock frequency.

For a more dramatic effect, two flip-flops in toggle mode produce a 4-state sequence; combinational logic on the two outputs decodes which lights to illuminate at each phase. With four states you can do pattern A-B-A-B (alternation) or A-AB-B-AB (four phases), depending on how the outputs are decoded.

This is the simplest possible synchronous sequential circuit — state changes only on clock edges, the state determines the output, and the output is observable as a deterministic time-varying pattern. It's the seed of finite-state machines and clocked control logic.

逐步尝试

在上方嵌入式电路中设置输入，然后阅读预期结果并验证。

1

Clock = running at 1 Hz

预期: Lights alternate at 0.5 Hz

您将看到: The two lights swap on every clock edge — one on, one off. Each light's frequency is half the clock's.
2

Clock = stopped

预期: Lights frozen

您将看到: Stop the clock — pattern freezes wherever it is. Sequential circuits need a clock to evolve.
3

Clock = running at 10 Hz

预期: Faster alternation, 5 Hz visible

您将看到: Increase the clock frequency — the lights blink faster. The relationship is exactly clock_freq / 2.
4

Clock = single edge

预期: Lights swap once

您将看到: A single clock pulse produces a single state transition. Sequential logic responds to edges, not levels.

使用的组件

实际应用

Real railroad crossing lights. Modern crossings use microcontroller-driven LED arrays, but the alternating-light behaviour is exactly what this circuit demonstrates.

Construction-site warning lights. Yellow flashers on barriers alternate at a fixed rate — same clock-divided toggle pattern.

Heartbeat / activity LEDs. A microcontroller's activity LED blinks at a fixed rate to confirm the system is alive — implemented as a counter divided down to a slow clock.

PWM-driven LED brightness. A clock divides the system clock down to a PWM frequency that controls duty cycle for analog-style brightness — same clock-divider principle.

Synchronous traffic light controllers. Real traffic lights use FSMs clocked at 1 Hz or so; the alternating crossing-light pattern is a one-state FSM specialization.

常见问题

Why do the lights alternate instead of both flashing on and off together?

Because one is driven by Q and the other by ¬Q (the complement). When Q toggles, Q goes 0→1 while ¬Q goes 1→0 — the lights swap.

How would I make the pattern slower?

Either reduce the clock frequency, or add more divide-by-2 stages (more T flip-flops in series) to divide the clock further. Cascading 4 flip-flops gives clock/16; cascading 6 gives clock/64.

Could I make a 3-light pattern?

Yes — use a 2-bit counter (two T flip-flops) and decode the 4 states with combinational logic to drive 3 lights in a pattern like A-AB-B-AB. Or 3 lights in a circle with a 3-state FSM.

How is this different from a standard counter?

It's a 1-bit counter (one toggle flip-flop). A wider counter has more bits and counts higher; this one toggles between two states only. The principles (clock-driven state transitions) are identical.

What if the clock has glitches?

Each glitch could cause an extra toggle. Real designs use clean clock generators and sometimes add Schmitt-trigger inputs to filter noise. In a simulator, you can assume the clock is glitch-free.