4-Bit SISO Shift Register Circuit Simulator

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Was du lernst

Distinguish SISO from SIPO shift register configurations.
Recognize the 4-cycle latency from input to output for a 4-bit SISO.
Apply SISO as a delay line for signal alignment.
Use SISO in FIR filters and clock-domain synchronizers.
Understand that SISO hides internal state — only input and output are visible.

So funktioniert es

A SISO (Serial-In Serial-Out) shift register has one serial input and one serial output, with N flip-flops in between as a delay chain. Bits entered at the input emerge at the output exactly N clock cycles later. The internal state of the register isn't directly visible — only the output pin tells you what came out.

This configuration is the most basic delay line in digital design. Useful when you need to align a fast signal with a slower one by a fixed number of cycles, or when implementing pipelines where a value must wait N cycles before being used.

For a 4-bit SISO register: - Cycle 0: Input bit 0 captured into FF0. - Cycle 1: FF0 → FF1; new input → FF0. - Cycle 2: FF1 → FF2; ... - Cycle 3: FF2 → FF3; ... - Cycle 4: FF3 → output.

So the bit you put in on cycle 0 emerges on the output at cycle 4 (or cycle 5 depending on whether the output samples after the shift). 4 cycles of latency.

SISO registers are also the basis of digital filters — a tapped delay line can implement FIR filters by adding weighted contributions from each tap.

Schritt für Schritt ausprobieren

Stelle die Eingänge in der Einbettung oben ein, lies was passieren sollte und überprüfe es.

1

Serial in = 1 then 0 0 0 Clock = 4 edges

Erwartet: Output = 1 on the 4th edge

Was du siehst: Single 1 input followed by 0s. The 1 walks through the register and emerges 4 cycles later.
2

Serial in = 1 0 1 0 ... Clock = running

Erwartet: Output = same alternating pattern, 4 cycles delayed

Was du siehst: Pattern emerges intact but offset in time. The SISO register is acting as a 4-cycle delay line.
3

Serial in = 0 always Clock = running

Erwartet: Output = 0

Was du siehst: Sustained 0 input → output stays 0 (after initial register flush). Steady-state behavior matches the input.
4

Serial in = 1 always Clock = running

Erwartet: Output = 1 (after 4 cycles)

Was du siehst: Sustained 1 input → after 4 cycles the register fills with 1s, output goes high. Steady-state is also a wire — just 4 cycles late.

Verwendete Komponenten

Shift Register (SISO)

×1

Output Light

×1

Praxisanwendungen

Pipeline alignment. When two signals need to arrive at the same downstream gate but one is N cycles ahead, a SISO register delays the early one to align them.

FIR filter delay lines. Each tap of a finite-impulse-response filter is one stage of a SISO register, multiplied by a coefficient.

Synchronizers. Crossing clock domains uses 2-stage SISO registers (the standard "two flop" synchronizer) to reduce metastability risk.

Token rings and circular buffers. A SISO with output fed back to input forms a circular delay buffer of fixed size.

Signature analyzers. BIST signature compression uses SISO with feedback to compute a CRC-like signature of test responses.

Häufig gestellte Fragen

Why is the latency exactly N cycles?

Each flip-flop adds one cycle of delay. With N flip-flops in series, total latency is N cycles. For a 4-bit SISO, that's 4 clocks from input to output.

Can I make this longer or shorter?

Just add or remove flip-flops. An 8-stage SISO has 8 cycles of delay; a 1-stage SISO is just a D flip-flop with 1 cycle delay. Latency scales linearly with the number of stages.

How is this used in clock-domain crossing?

Two-flop synchronizers — a 2-stage SISO running in the destination clock domain. The first flop captures the foreign signal (potentially metastable); the second flop samples it after the metastability has resolved. Standard pattern for safe domain crossing.

Is the propagation delay the same regardless of input value?

Yes, mostly. Each flip-flop has a clock-to-Q delay roughly independent of input value. For 4 stages, total propagation is 4 cycles + 4 × clock-to-Q ≈ 4 cycles in steady-state operation.

Could I tap intermediate stages for a tapped delay line?

Yes — that's a SIPO + extra logic. Each tap exposes one flip-flop's Q to a multiplier and accumulator, building an FIR filter. Pure SISO hides the taps; tapped-SISO exposes them for multi-tap signal processing.