2-Bit Full Adder Chain
Two-bit full adder with carry propagation. Learn how full adders chain together for multi-bit arithmetic.
배울 내용
- Chain two full-adder cells for 2-bit binary addition.
- Tie bit 0's Cin to 0 to make a full-adder behave like a half-adder.
- Trace the carry chain Cin0 → Cout0 → Cin1 → Cout1.
- Recognise why uniform full-adder cells beat half + full chains for scaling.
- Apply this pattern to wider ripple-carry ALUs.
작동 원리
This 2-bit ripple-carry adder uses two full-adders in series — both stages identical, with the carry-out of bit 0 feeding the carry-in of bit 1. Bit 0's carry-in is tied to 0 (no carry from below).
Unlike the half-adder + full-adder pattern, here both bits use the same kind of cell. This trades a couple of extra transistors at bit 0 for uniformity: every stage looks identical, simplifying scaling to wider adders. Real production ALUs use this all-full-adder pattern because it makes the layout regular.
For each bit i: - Si = Ai ⊕ Bi ⊕ Cini - Couti = AiBi + Cini(Ai ⊕ Bi)
The final result is the 3-bit number (Cout, S1, S0). The carry chain Cin0 → Cout0 → Cin1 → Cout1 is the critical path that limits speed in wide adders.
진리표
Same I/O as the half + full version, but every stage is a full-adder. Showing key rows from the 16-row table.
| 입력 | 출력 | ||||||
|---|---|---|---|---|---|---|---|
| A1 | A0 | B1 | B0 | Cout | S1 | S0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 + 0 = 0 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 + 1 = 2 (carry from bit 0) |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 3 + 1 = 4 (longest carry chain) |
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 2 + 2 = 4 |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 3 + 3 = 6 (max) |
불 대수식
Per-stage sum (full-adder).
Per-stage carry — majority of the three inputs.
Inter-stage wiring of the carry chain.
단계별로 시도해 보세요
위 임베드에서 입력을 설정한 후, 예상 결과를 읽고 직접 확인하세요.
- 1A = 01 B = 01예상:
Cout S1 S0 = 010관찰 포인트: 1 + 1 = 2. Bit 0 generates carry; bit 1 sum is 1. - 2A = 11 B = 01예상:
Cout S1 S0 = 100관찰 포인트: 3 + 1 = 4. Carry ripples bit 0 → bit 1 → Cout. - 3A = 10 B = 11예상:
Cout S1 S0 = 101관찰 포인트: 2 + 3 = 5. Mixed carry pattern through both stages. - 4A = 11 B = 11예상:
Cout S1 S0 = 110관찰 포인트: 3 + 3 = 6 — every stage carries; result needs all 3 output bits.
사용된 구성 요소
실제 응용 사례
Generic ALU building block. Wider ALUs scale this exact pattern by chaining N full-adders, with bit 0's Cin tied to 0 (or to the subtract control for two's complement subtraction).
Multi-precision arithmetic. When adding numbers wider than the native ALU width, software (or hardware) chains additions and forwards the carry-out as the next chunk's carry-in.
Carry-save adder cells. In multipliers, full-adder cells form a 2D array that compresses partial products before a final ripple-carry stage.
Increment/decrement units. A counter increment is just adder with B = 0...01 — same chained-full-adder structure.