2-Bit Full-Adder Chain Circuit Simulator

您将学到什么

Chain two full-adder cells for 2-bit binary addition.
Tie bit 0's Cin to 0 to make a full-adder behave like a half-adder.
Trace the carry chain Cin0 → Cout0 → Cin1 → Cout1.
Recognise why uniform full-adder cells beat half + full chains for scaling.
Apply this pattern to wider ripple-carry ALUs.

工作原理

This 2-bit ripple-carry adder uses two full-adders in series — both stages identical, with the carry-out of bit 0 feeding the carry-in of bit 1. Bit 0's carry-in is tied to 0 (no carry from below).

Unlike the half-adder + full-adder pattern, here both bits use the same kind of cell. This trades a couple of extra transistors at bit 0 for uniformity: every stage looks identical, simplifying scaling to wider adders. Real production ALUs use this all-full-adder pattern because it makes the layout regular.

For each bit i: - Si = Ai ⊕ Bi ⊕ Cini - Couti = AiBi + Cini(Ai ⊕ Bi)

The final result is the 3-bit number (Cout, S1, S0). The carry chain Cin0 → Cout0 → Cin1 → Cout1 is the critical path that limits speed in wide adders.

真值表

Same I/O as the half + full version, but every stage is a full-adder. Showing key rows from the 16-row table.

输入				输出
A1	A0	B1	B0	Cout	S1	S0
0	0	0	0	0	0	0	0 + 0 = 0
0	1	0	1	0	1	0	1 + 1 = 2 (carry from bit 0)
1	1	0	1	1	0	0	3 + 1 = 4 (longest carry chain)
1	0	1	0	1	0	0	2 + 2 = 4
1	1	1	1	1	1	0	3 + 3 = 6 (max)

布尔表达式

S_i = A_i \oplus B_i \oplus C_{in,i}

Per-stage sum (full-adder).

C_{out,i} = A_i B_i + C_{in,i}(A_i \oplus B_i)

Per-stage carry — majority of the three inputs.

C_{in,1} = C_{out,0},\;\; C_{in,0} = 0

Inter-stage wiring of the carry chain.

逐步尝试

在上方嵌入式电路中设置输入，然后阅读预期结果并验证。

1

A = 01 B = 01

预期: Cout S1 S0 = 010

您将看到: 1 + 1 = 2. Bit 0 generates carry; bit 1 sum is 1.
2

A = 11 B = 01

预期: Cout S1 S0 = 100

您将看到: 3 + 1 = 4. Carry ripples bit 0 → bit 1 → Cout.
3

A = 10 B = 11

预期: Cout S1 S0 = 101

您将看到: 2 + 3 = 5. Mixed carry pattern through both stages.
4

A = 11 B = 11

预期: Cout S1 S0 = 110

您将看到: 3 + 3 = 6 — every stage carries; result needs all 3 output bits.

使用的组件

实际应用

Generic ALU building block. Wider ALUs scale this exact pattern by chaining N full-adders, with bit 0's Cin tied to 0 (or to the subtract control for two's complement subtraction).

Multi-precision arithmetic. When adding numbers wider than the native ALU width, software (or hardware) chains additions and forwards the carry-out as the next chunk's carry-in.

Carry-save adder cells. In multipliers, full-adder cells form a 2D array that compresses partial products before a final ripple-carry stage.

Increment/decrement units. A counter increment is just adder with B = 0...01 — same chained-full-adder structure.

常见问题

Why use full-adders for both bits instead of half + full?

Uniformity. Every stage is identical, simplifying layout and timing closure for wide adders. The slight extra cost at bit 0 (a full-adder vs half-adder) is small compared to the engineering benefit of regular structure.

What's the carry chain's role?

It propagates the carry from each bit position to the next. Bit i+1 cannot finish computing its sum until bit i's carry-out is ready. This serial dependency is the slowest path in any ripple-carry adder.

How do I extend to 4 or 8 bits?

Add more full-adders to the chain. Each new bit's Cin = previous bit's Cout. Worst-case delay grows linearly with bit width — that's the price of ripple-carry simplicity.

Is this slow compared to carry-lookahead adders?

For 2 bits, no — the chain is too short to benefit from lookahead. For 32+ bits, lookahead is dramatically faster because it computes carries in parallel rather than serially.

How is subtraction handled?

Two's complement: invert B and set Cin0 to 1 (instead of 0). The same chain computes A − B. Real ALUs include XOR gates on the B inputs controlled by an add/subtract control bit.