2-Bit Binary Adder
Two-bit binary addition with carry propagation. Demonstrates multi-bit arithmetic using basic gates and carry chain.
学べること
- Add two 2-bit numbers using a half-adder + full-adder cascade.
- Trace the carry chain through bit 0 and bit 1.
- Read the truth table of all 16 input combinations and verify the binary sum.
- Recognize the ripple-carry pattern's serial bottleneck.
- Apply this slice to wider ALUs by chaining more full-adders.
仕組み
This 2-bit binary adder takes two 2-bit operands (A1 A0 + B1 B0) and produces a 3-bit result (Cout S1 S0). The construction is the textbook ripple-carry pattern: a half-adder for bit 0, a full-adder for bit 1, with bit 0's carry feeding bit 1's carry-in.
For each bit i: Si = Ai ⊕ Bi ⊕ Cini (sum, parity-style); Couti = AiBi + Cini(Ai ⊕ Bi) (carry-out, majority-style). Bit 0's Cin is tied to 0.
The maximum sum is 11 + 11 = 110 (3 + 3 = 6) — three output bits accommodate the overflow.
This is the same ripple-carry pattern that scales to 32 or 64 bits in production CPUs, just narrower. The critical path runs through the carry chain: each bit must wait for the carry from the bit below.
真理値表
Showing key rows. Full table has 16 input combinations.
| 入力 | 出力 | ||||||
|---|---|---|---|---|---|---|---|
| A1 | A0 | B1 | B0 | Cout | S1 | S0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 + 0 = 0 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 + 1 = 2 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 2 + 1 = 3 |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 3 + 1 = 4 (carry) |
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 2 + 2 = 4 |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 3 + 3 = 6 (max) |
ブール式
Bit 0 (half-adder).
Bit 1 sum (full-adder).
Bit 1 carry-out — propagates to a third output bit.
順を追って試す
上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。
- 1A = 01 B = 01期待値:
Cout S1 S0 = 010観察ポイント: 1 + 1 = 2. Carry from bit 0 makes S1=1. - 2A = 10 B = 10期待値:
Cout S1 S0 = 100観察ポイント: 2 + 2 = 4. Bit 1's full-adder generates the overflow. - 3A = 11 B = 01期待値:
Cout S1 S0 = 100観察ポイント: 3 + 1 = 4. Carry ripples through both stages to Cout. - 4A = 11 B = 11期待値:
Cout S1 S0 = 110観察ポイント: 3 + 3 = 6 — maximum 2-bit sum needs 3 output bits.
使用コンポーネント
実世界での応用
ALU bit-slice. This adder is a 2-bit slice of any wider integer ALU. CPUs build 32- or 64-bit adders from chained slices like this.
Counter logic. Add 1 to a counter each clock edge using exactly this adder structure (with B fixed to 0...01).
Address generators. Memory addressing — base + offset — is wide-integer addition. Same chained-full-adder pattern.
DSP accumulators. Sum of products in DSP loops uses adders for each accumulation step.