Template: 2-to-1 Multiplexer
Basic 2-input multiplexer with select control. Foundation for data selection and routing circuits.
Lo que aprenderás
- Use a single select bit to route one of two data inputs to the output.
- Read the 2-to-1 MUX truth table — output follows D0 when S=0, D1 when S=1.
- Write the SOP Boolean expression: Y = ¬S·D0 + S·D1.
- Recognise MUXes inside ALUs, FPGAs, and bus arbiters.
- Understand that any 2ⁿ-row truth table can be realised by a 2ⁿ-to-1 MUX.
Cómo funciona
A multiplexer (MUX) is a digital data selector — "pick one of N inputs and route it to the output, based on a select signal." The 2-to-1 MUX is the smallest case: two data inputs (D0, D1), one select line (S), one output (Y).
The rule: when S = 0, Y follows D0. When S = 1, Y follows D1. The select line is the "steering wheel" — flip it to redirect which data input reaches the output.
Boolean expression: Y = (¬S · D0) + (S · D1). Read this as: "output equals D0 if S is 0 (the first AND term fires), or D1 if S is 1 (the second AND term fires)." This is the classic Sum-of-Products form.
A 2-to-1 MUX needs ⌈log₂(2)⌉ = 1 select bit. A 4-to-1 MUX needs 2 select bits to address its 4 inputs; an 8-to-1 needs 3. Multiplexers scale logarithmically — a key reason they're efficient compared to brute-force routing.
MUXes are also a fundamental primitive for synthesis: any 2ⁿ-row truth table can be implemented as a 2ⁿ-to-1 MUX with the input variables as select lines and the truth-table output values wired to the data inputs. This is why FPGAs are essentially seas of small MUXes (in look-up table form).
Tabla de verdad
S selects which data input passes through. Showing all 8 (S, D0, D1) combinations.
| Entradas | Salida | |||
|---|---|---|---|---|
| S | D0 | D1 | Y | |
| 0 | 0 | 0 | 0 | S=0 → Y=D0=0 |
| 0 | 0 | 1 | 0 | S=0 → Y=D0=0 (D1 ignored) |
| 0 | 1 | 0 | 1 | S=0 → Y=D0=1 |
| 0 | 1 | 1 | 1 | |
| 1 | 0 | 0 | 0 | S=1 → Y=D1=0 (D0 ignored) |
| 1 | 0 | 1 | 1 | S=1 → Y=D1=1 |
| 1 | 1 | 0 | 0 | |
| 1 | 1 | 1 | 1 | |
Expresión booleana
Sum-of-products form. Each AND term "selects" one data input based on S.
Ternary operator notation — same logic, conditional read.
Pruébalo paso a paso
Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.
- 1S = 0 D0 = 1 D1 = 0Esperado:
Y = 1Lo que verás: S=0 selects D0. Output follows D0 (=1). D1 is ignored. - 2S = 0 D0 = 0 D1 = 1Esperado:
Y = 0Lo que verás: S=0 still selects D0. D1's value doesn't affect Y. - 3S = 1 D0 = 1 D1 = 0Esperado:
Y = 0Lo que verás: Flipping S to 1 switches the steering — now D1 is selected. D0 is ignored. - 4S = 1 D0 = 0 D1 = 1Esperado:
Y = 1Lo que verás: S=1, D1=1 — output is 1. The MUX has transparently routed the chosen input through.
Componentes utilizados
Aplicaciones en el mundo real
ALU operation selection. A CPU's ALU uses MUXes to choose between adder, shifter, and logic-unit outputs based on the instruction's opcode.
Bus arbitration. Multiple sources compete for a shared bus; a MUX selects which source's data reaches the destination based on a grant signal.
FPGA look-up tables. Each FPGA logic cell is essentially a 4-input or 6-input MUX whose data inputs are programmed as the truth-table values of the desired function.
Conditional execution in CPUs. "If condition then x = a else x = b" compiles to a MUX that selects a or b based on the condition flag. Many ARM and RISC-V instructions use this directly (CMOV).
Network packet routing. Switches use MUXes to direct each incoming packet to the appropriate outgoing port based on routing-table lookup.