1-to-4 Demultiplexer Circuit Simulator

インタラクティブシミュレーターには JavaScript が必要です

JavaScript を有効にするとライブ回路が読み込まれます。下の真理値表で動作を確認できます。

学べること

Use a 2-bit select to route one input to one of 4 outputs.
Read the 1-to-4 DEMUX behaviour table — only one output is active at a time.
Derive the per-output Boolean expressions as AND of D with select-decode.
Recognise the equivalence: DEMUX with D=1 is a 2-to-4 decoder.
Apply 1-to-4 DEMUXes for memory-bank routing and chip-select fan-out.

仕組み

A 1-to-4 demultiplexer routes one data input D to one of four outputs (Y0–Y3), based on a 2-bit select code (S1, S0). The selected output equals D; the other three are 0.

Mapping: - S1S0 = 00 → Y0 = D, others = 0 - S1S0 = 01 → Y1 = D, others = 0 - S1S0 = 10 → Y2 = D, others = 0 - S1S0 = 11 → Y3 = D, others = 0

Boolean: each output ANDs D with the matching minterm of the select bits. Y0 = ¬S1·¬S0·D, Y1 = ¬S1·S0·D, Y2 = S1·¬S0·D, Y3 = S1·S0·D.

With D held high, the DEMUX becomes a 2-to-4 decoder — useful for chip-select and address decoding. With D varying, it's a router for distributing one signal to one of four destinations based on select.

真理値表

Three input combinations to focus on: D=1 with each of the four select codes. With D=0, all outputs are 0.

入力			出力
S1	S0	D	Y0	Y1	Y2	Y3
0	0	1	1	0	0	0	Select 00 → Y0 receives D
0	1	1	0	1	0	0	Select 01 → Y1 receives D
1	0	1	0	0	1	0	Select 10 → Y2 receives D
1	1	1	0	0	0	1	Select 11 → Y3 receives D
0	0	0	0	0	0	0	D=0 — all outputs 0

ブール式

Y_0 = \overline{S_1}\overline{S_0}D,\;\; Y_1 = \overline{S_1}S_0 D

Outputs 0 and 1: each ANDs D with the matching select decode.

Y_2 = S_1\overline{S_0}D,\;\; Y_3 = S_1 S_0 D

Outputs 2 and 3 — the upper half of the select range.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

S1 = 0 S0 = 0 D = 1

期待値: Y0=1, others=0

観察ポイント: Select 00, D=1 → only Y0 lights up. The other outputs stay dark.
2

S1 = 1 S0 = 0 D = 1

期待値: Y2=1, others=0

観察ポイント: Walk through the select codes — each one routes D to a different output.
3

S1 = 1 S0 = 1 D = 0

期待値: All outputs = 0

観察ポイント: Selected output is Y3, but D=0, so Y3 is 0. The DEMUX is doing its job — non-selected lines are guaranteed 0.
4

S1 = 0 S0 = 1 D = 1

期待値: Y1=1, others=0

観察ポイント: Y1 lights, others stay dark. Try toggling D rapidly while keeping S fixed — only Y1 reflects D.

使用コンポーネント

Input Switch

×3

Demultiplexer (1-to-4)

×1

Output Light

×4

実世界での応用

Memory bank write enable. A 2-bit bank selector routes a write-enable pulse to one of 4 memory banks via a 1-to-4 DEMUX.

TDM serial routing. A 4-channel TDM receiver uses a 1-to-4 DEMUX clocked synchronously with the sender to split the time-multiplexed stream back into 4 channels.

State-machine output routing. A FSM in a one-hot encoding routes a common output strobe to the active state's destination via a DEMUX driven by the state select.

Chip-select fan-out. A microcontroller with 4 peripherals can use a 1-to-4 DEMUX to assert exactly one peripheral's chip-select line based on the address-decode result.

よくある質問

How is this different from a 2-to-4 decoder?

A decoder has no data input — it just asserts one of N output lines based on select. A DEMUX with D=1 behaves identically. With varying D, the DEMUX additionally passes D's value (not just 1) to the selected output.

Can two outputs be high at once?

No. A DEMUX guarantees exactly one output reflects D; all others are 0. This is by construction — only one minterm of the select bits is 1 at a time.

What's the gate-delay depth through a 1-to-4 DEMUX?

About 2 to 3 gate delays. The select decoder is one or two layers (NOTs + ANDs); the per-output AND with D adds one more. Compact for routing logic.

How does this scale to 1-to-N for arbitrary N?

1-to-N needs ⌈log₂N⌉ select bits and N output lines. For powers of 2, you can build it as a tree of 1-to-2 DEMUXes — log₂N levels deep, total of N−1 1-to-2 stages.

Where does DEMUX appear in a CPU?

Write-back stage uses DEMUX to route the result to the correct register based on the destination-register field of the instruction. Cache-line fill uses DEMUX to direct the bus data to the correct way of a set-associative cache.