SR Latch Demonstration
Set-Reset latch with S and R inputs. Learn basic memory storage using cross-coupled gates and bistable operation.
您将学到什么
- Identify the SR latch as the simplest memory element.
- Recognize the four input combinations: Set, Reset, Hold, Forbidden.
- Trace the cross-coupled feedback that creates bistable storage.
- Distinguish level-sensitive latches from edge-triggered flip-flops.
- Apply SR latches to debounce, arbitration, and SRAM cells.
工作原理
An SR latch is the simplest memory element — two cross-coupled NOR (or NAND) gates that can hold one bit indefinitely. It has two inputs (S = Set, R = Reset) and two complementary outputs (Q, ¬Q). The cross-coupling creates a bistable feedback loop: when both inputs are quiet, whatever value is currently on Q stays there.
NOR-based active-high SR latch behaviour: - Set (S=1, R=0): Q goes to 1 (and stays there after S returns to 0). - Reset (S=0, R=1): Q goes to 0 (and stays there). - Hold (S=0, R=0): Q keeps its previous value — the latch "remembers." - Forbidden (S=1, R=1): Both inputs high force both outputs to 0 simultaneously, breaking the Q = ¬Q invariant. When inputs return to 00 the final state depends on which input releases last — non-deterministic.
The SR latch is the seed of all sequential logic. Every flip-flop, register, and SRAM cell starts with two cross-coupled inverters (effectively a SR latch with hidden control). Latches were used as registers throughout early CPUs before edge-triggered flip-flops became dominant.
Key insight: latches are level-sensitive (output reflects input continuously while enabled), unlike flip-flops which are edge-triggered (output samples only on a clock edge).
真值表
SR latch behaviour table. Q' is the previous Q value (memory). Forbidden state when S=R=1.
| 输入 | 输出 | |||
|---|---|---|---|---|
| S | R | Q | Behaviour | |
| 0 | 0 | 0 | Hold — Q stays at previous value | |
| 0 | 1 | 0 | Reset — Q forced to 0 | |
| 1 | 0 | 1 | Set — Q forced to 1 | |
| 1 | 1 | 0 | Forbidden — both outputs go to 0, invariant broken | |
布尔表达式
Next-state equation: Q is set if S asserted, kept if Reset is low, cleared if Reset asserted.
Cross-coupled NOR implementation. The two outputs feed each other's NOR inputs.
逐步尝试
在上方嵌入式电路中设置输入，然后阅读预期结果并验证。
- 1S = 1 R = 0预期:
Q = 1您将看到: Set the latch — Q goes high. Now release S back to 0 and Q stays high. The latch remembers. - 2S = 0 R = 0预期:
Q unchanged您将看到: After setting, both inputs low → latch holds. Q stays at whatever it was. This is the memory function. - 3S = 0 R = 1预期:
Q = 0您将看到: Reset — Q drops to 0. Release R and Q stays at 0. Latch now in the reset state, awaiting next Set. - 4S = 1 R = 1预期:
Both Q and ¬Q = 0 (forbidden)您将看到: Forbidden state — the latch breaks its Q = ¬Q invariant. When inputs return to 00, the final state is unpredictable. Avoid in real designs.
使用的组件
实际应用
SRAM cell. A 6-transistor SRAM cell is two cross-coupled inverters with access transistors — functionally an SR latch with bit-line control. Every byte of cache memory in a modern CPU is millions of these.
Bus master arbitration. A two-master arbiter often uses an SR latch where Set comes from master A's request and Reset comes from master B's. The latch state determines who currently owns the bus.
Push-button debouncing. A bouncing physical switch generates multiple transitions; an SR latch with the bounce-up signal on Set and bounce-down on Reset filters noise into a single clean transition.
Manual reset circuits. Many embedded systems use SR latches to capture power-on reset until firmware acknowledges and clears it.
Race-condition detectors. Two parallel signals racing into Set and Reset; whichever wins determines the latch state. Used in metastability detectors and arbiter circuits.