Digital Lock Security System Circuit Simulator

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Activa JavaScript para cargar el circuito en vivo. La tabla de verdad de abajo describe el comportamiento del circuito.

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Lo que aprenderás

Compare two multi-bit buses using per-bit XNOR.
AND-reduce per-bit matches for an all-bits-equal signal.
Recognise XNOR's role as the single-bit equality detector.
Apply the XNOR-AND pattern in cache tags, address decoding, and locks.
Understand why pure XNOR matching is insufficient for cryptographic security.

Cómo funciona

A digital lock verifies a multi-bit password against a stored value and unlocks only when every bit matches. The circuit uses per-bit XNOR comparison (XOR followed by NOT, or a direct XNOR gate) plus an AND-reduce: every bit must match for the unlock signal to fire.

For a 4-bit password, four XNORs compare each input bit to its expected value. The AND of all four XNORs is high only when every comparison reports "match." This is the same pattern as a bus equality comparator — but with one of the buses being the stored password (typically wired as constants).

More advanced locks add features: an enable input that gates the unlock (locked mode vs. armed mode), a mismatch counter that triggers a lockout after N failed attempts, or a timeout that re-locks after a delay. The core matching logic stays the same — XNOR per bit, AND across all bits.

Real electronic locks add cryptographic protection (challenge-response, signed tokens) so an attacker can't simply read the wires. Pure XNOR matching is suitable for educational and low-security applications.

Tabla de verdad

Stored password is fixed at 1010 (= 10 decimal). Lock fires only when input bits exactly match.

Entradas				Salida
I3	I2	I1	I0	Unlock
0	0	0	0	0	Wrong password
1	0	1	0	1	Match — unlock
1	0	1	1	0	One bit wrong (LSB) — locked
0	1	0	1	0	Inverted password — locked (max mismatch)
1	1	1	0	0	One bit wrong (bit 2) — locked

Expresión booleana

\text{Match}_i = I_i \odot P_i = I_i \oplus P_i \;\overline{}

Per-bit XNOR with the stored password bit Pi.

\text{Unlock} = \bigwedge_{i=0}^{N-1} \text{Match}_i

AND-reduce across all per-bit matches. Single mismatch sinks the unlock.

Pruébalo paso a paso

Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.

1

I = 0000

Esperado: Unlock = 0

Lo que verás: All zeros doesn't match the stored password (1010). Lock stays closed.
2

I = 1010

Esperado: Unlock = 1

Lo que verás: All four bits match — the unlock light turns on. The single permitted combination of 16.
3

I = 1011

Esperado: Unlock = 0

Lo que verás: One bit off (LSB). The XNOR for bit 0 reports mismatch; the AND drops to 0; lock stays closed.
4

I = 0101

Esperado: Unlock = 0

Lo que verás: Inverted from the password (every bit wrong). Maximum mismatch. Unlock stays low.

Componentes utilizados

Aplicaciones en el mundo real

Combination lock keypads. A user enters a code; per-digit XNOR comparators verify each digit against the stored combination.

Address decoders. Memory-mapped peripherals respond when their address bus matches a hardcoded base — implemented as XNOR-AND comparators.

Password verification in microcontrollers. A bootloader reads an EEPROM password and compares it against user input via the same XNOR-AND pattern.

Cache tag matching. Cache lookups compare the address tag against stored tags; a match (all-XNORs-high) means cache hit.

State-machine condition matching. A FSM transitions when the input pattern matches a stored expected pattern — same XNOR-AND verifier.

Preguntas frecuentes

Why XNOR instead of XOR?

XNOR fires when bits match; XOR fires when they differ. For a lock you want a signal that's high on match. You could equivalently use XOR + AND-of-inverses, but XNOR-AND is more direct.

How does this scale to longer passwords?

One XNOR per bit + an N-input AND. A 64-bit password uses 64 XNORs and a 64-input AND-tree. Comparator depth grows logarithmically; per-bit comparator count grows linearly.

Why is this not secure for real applications?

An attacker reading the wires sees the password directly. Real digital locks use cryptographic protocols — challenge-response, signed tokens, hashing — that don't transmit the secret in cleartext. The XNOR-AND pattern is the underlying primitive but needs cryptographic wrapping.

Could I add a 'wrong attempt' counter?

Yes — register the unlock signal's negation each time the user submits, and feed an inverted-OR (any-mismatch) into a counter. After N failed attempts, latch a lockout state. Most digital locks do exactly this to prevent brute-force.

What's the difference between this and an address decoder?

Mechanically the same: XNOR-AND match against a stored constant. The difference is application — locks expose the constant as a hardcoded password; address decoders expose it as the chip's address. Same gates, different label.