Basic D Latch
Simple D latch with data and enable inputs. Introduction to digital memory storage and transparent latch operation.
Lo que aprenderás
- Recognize the D latch as a single-data-input memory element.
- Understand how the D latch eliminates the SR latch's forbidden state.
- Distinguish transparent mode (enable = 1, Q follows D) from hold mode (enable = 0, Q frozen).
- Connect the D latch's structure to its underlying SR latch.
- Identify D latches as the simplest building block for registers.
Cómo funciona
A D latch ('Data latch' or 'Delay latch') solves the SR latch's forbidden-state problem by replacing two control inputs (S, R) with a single data input D plus an enable. When enable is high, Q = D (transparent mode); when enable is low, Q holds its last value (latched).
Internal construction: D feeds an inverter; D and ¬D become the S and R inputs of an underlying SR latch. With this wiring, S and R are always opposites — the forbidden state (S=R=1) cannot be reached. Hence the D latch is safer for general use.
In this 'basic' version (no clock), the enable is implicit — the latch is always transparent: whatever D is, Q reflects it. To make the latch actually store a value, you need an enable that can go low to freeze the state. That's the next template (D Latch with Clock).
The D latch is the building block of every register: store one bit per latch, fan in N latches for N-bit storage. Modern flip-flops (edge-triggered) refine this further — they sample only on a clock edge instead of being continuously transparent.
Tabla de verdad
Basic D latch (always transparent, no enable). Q always equals D.
| Entradas | Salida | ||
|---|---|---|---|
| D | Q | ¬Q | |
| 0 | 0 | 1 | D=0 → Q=0 |
| 1 | 1 | 0 | D=1 → Q=1 |
Expresión booleana
Transparent latch: output follows input directly. The SR forbidden state is impossible because S and R are derived from D and ¬D — never both high.
Pruébalo paso a paso
Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.
- 1D = 0Esperado:
Q = 0, ¬Q = 1Lo que verás: D = 0 → Q = 0 immediately. The latch is always transparent (no clock to gate it). - 2D = 1Esperado:
Q = 1, ¬Q = 0Lo que verás: D = 1 → Q = 1. Output follows input with only gate-propagation delay.
Componentes utilizados
Aplicaciones en el mundo real
Latched outputs of decoders. Address decoders sometimes feed latched outputs so glitchy address transitions don't propagate as multiple chip-select pulses.
Pipelined processor stages. Older pipelined CPUs used D latches between stages to hold values for the next clock; modern CPUs use edge-triggered flip-flops instead.
Configuration register storage. Configuration bits set during initialization can use D latches with a one-time enable pulse to freeze the value.
Holding peripheral data. A peripheral whose output bus is read once per cycle can use D latches with the bus-strobe as enable.
Educational stepping stone. D latches are introduced before D flip-flops because they're simpler internally — once you understand transparency vs. holding, edge triggering follows naturally.