3-Bit Binary Adder Circuit Simulator

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仕組み

真理値表

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Chain three full-adders to add two 3-bit numbers.
Compute sums up to 7 + 7 = 14 in binary.
Read the truth table of selected key rows.
Trace the carry chain across 3 stages.
Recognise this as a ripple-carry adder — same pattern at any bit width.

A 3-bit binary adder adds two 3-bit operands (range 0–7 each) and produces a 4-bit result (range 0–14, plus the special case 7+7=14). It chains three full-adder cells: bit 0 with carry-in tied to 0, bits 1 and 2 each receiving the previous bit's carry-out as their carry-in. The final carry-out becomes the high (4th) bit of the result.

Boolean per stage: - Si = Ai ⊕ Bi ⊕ Cini - Couti = AiBi + Cini(Ai ⊕ Bi)

The ripple-carry adder is conceptually transparent — it implements grade-school addition exactly: add a column, carry to the next, repeat. The downside is the carry chain's serial dependency, which becomes a speed bottleneck at wide bit widths.

For 3 bits the maximum sum is 111 + 111 = 1110 (7 + 7 = 14), comfortably fitting in 4 output bits.

Selected rows from the 64 possible (A 0–7) × (B 0–7) combinations.

S_i = A_i \oplus B_i \oplus C_{in,i}

Per-stage sum bit.

C_{out,i} = A_i B_i + C_{in,i}(A_i \oplus B_i)

Per-stage carry-out.

S_3 = C_{out,2}

Top bit of the 4-bit result is bit 2's carry-out — the overflow into the 8s place.

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

A = 001 B = 001

期待値: S = 0010

観察ポイント: 1 + 1 = 2. Carry from bit 0 makes S1 = 1.
2

A = 100 B = 100

期待値: S = 1000

観察ポイント: 4 + 4 = 8. Bit 2 carries straight to S3.
3

A = 111 B = 001

期待値: S = 1000

観察ポイント: 7 + 1 = 8. Carry ripples through all 3 stages — the worst-case path.
4

A = 111 B = 111

期待値: S = 1110

観察ポイント: 7 + 7 = 14 — maximum 3-bit + 3-bit sum. Note the result fits exactly in 4 bits (0–15 range).

Tiny ALU bit-slice. Production CPUs build 32- or 64-bit adders from chains of full-adder cells exactly like this one, just longer.

Audio/video sample sums. 3-bit additions appear in early-stage signal processing where dynamic range is small, e.g., level meters or simple mixers.

Low-power sensor counters. Battery-powered devices counting events with limited range may use compact ripple-carry adders to save energy.

Educational stepping stone. A 3-bit adder is the smallest circuit where you see the full carry-propagation pattern — half + full + full chain.

3 + 1 = 4 (binary 100)

4 + 4 = 8 (binary 1000)

7 + 7 = 14 (max, binary 1110)

Why does 7 + 7 give a 4-bit result?

Because the result (14) is larger than the maximum 3-bit number (7). Adding two N-bit numbers can produce up to (N+1) bits — the carry-out is the (N+1)-th bit.

What's the worst-case delay?

Three full-adder delays in series. Each full-adder has ~3 internal gate delays, so worst-case ~9 gate delays for 3 bits. Linear in width.

Is overflow possible?

Only if you ignore the carry-out (S3) and force the result into 3 bits. Treating the result as a full 4-bit number, no overflow can occur for 3-bit + 3-bit addition.

How does this relate to subtraction?

A − B = A + (¬B + 1) using two's complement. Invert B and tie Cin0 to 1. Same hardware, different control. Most ALUs include this option.