8-Bit Serial Transmitter/Receiver Circuit Simulator

El simulador interactivo requiere JavaScript

Activa JavaScript para cargar el circuito en vivo. La tabla de verdad de abajo describe el comportamiento del circuito.

Abrir en el simulador Ver todas las plantillas

Lo que aprenderás

Use a PISO shift register to transmit a byte serially.
Use a SIPO shift register to receive a byte from a serial line.
Recognize that 8 clocks are needed to send one byte.
Understand the role of framing (start/stop bits, chip-select) in real protocols.
Apply this pattern to UART, SPI, JTAG, and modern SerDes.

Cómo funciona

An 8-bit serial transmitter/receiver moves byte-sized data over a single wire one bit at a time. The transmit side uses a PISO (parallel-in serial-out) shift register: load the byte in parallel, then shift it out one bit per clock. The receive side uses a SIPO (serial-in parallel-out) shift register: capture each bit as it arrives, and after 8 clocks the byte is reassembled.

For reliable communication: - Both sides must agree on the clock rate (or recover the clock from the data). - Some way to frame the byte boundaries — start bit, stop bit, or a separate select line. - Optional parity bit for error detection.

This circuit demonstrates the core mechanism without all the framing logic: a TX register, a wire, an RX register, and a shared clock. Loading a byte into TX and clocking 8 times moves it bit-by-bit to RX.

Real serial protocols add layers: - UART: Asynchronous, with start/stop bits framing each byte. - SPI: Synchronous, with separate clock line and chip-select for framing. - I²C: Synchronous, with start/stop conditions and acknowledgements. - USB / Ethernet / SerDes: High-speed differential signaling with embedded clock recovery.

All of them use shift registers as the fundamental TX/RX primitive.

Pruébalo paso a paso

Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.

1

TX_load = 01000001 (= 'A') Clock = 8 edges

Esperado: RX = 01000001

Lo que verás: Load 'A' into TX, clock 8 times — RX has captured all 8 bits in order. The byte has crossed the wire serially.
2

TX_load = 11111111 Clock = 8 edges

Esperado: RX = 11111111

Lo que verás: All-ones byte arrives at RX intact. Data integrity confirmed via shift-register transfer.
3

TX_load = 10101010 Clock = 8 edges

Esperado: RX = 10101010

Lo que verás: Alternating-bit pattern — common test pattern for verifying serial-link correctness.
4

TX_load = any Clock = fewer than 8 edges

Esperado: RX has partial data

Lo que verás: Stopping early leaves the byte half-transmitted. Real protocols use start/stop bits or chip-select to frame exactly 8 bits per byte and avoid this.

Componentes utilizados

Shift Register (8-bit)

Aplicaciones en el mundo real

UART debug ports. Almost every microcontroller has a UART for printing debug messages — internally TX/RX shift registers like this circuit.

SPI flash and SD card interfaces. Microcontrollers boot from SPI flash via shift registers running at tens of MHz; data flows byte-by-byte.

JTAG test interface. JTAG uses a long serial scan chain (one giant SISO shift register) to load test data and capture results across many chips on a board.

RS-232 / RS-485 industrial buses. Legacy industrial control buses use UART-style framing with shift-register TX/RX inside line-driver chips.

Ethernet PHYs. Gigabit Ethernet PHYs include high-speed shift registers as part of their SerDes, converting parallel MAC data to serial line signals at multi-Gbps.

Preguntas frecuentes

Why send data serially when parallel is faster?

Wires. A parallel 64-bit bus needs 64 wires + ground + clocks. A serial connection uses 1 (or 2 with differential signalling). For long distances or many devices, serial is far cheaper despite needing more clock cycles per byte.

How does the receiver know the byte boundaries?

Several methods: (1) **Start/stop bits** — UART frames each byte with a start (0) and stop (1) bit. (2) **Clock + chip-select** — SPI uses a separate clock line and asserts chip-select for the 8-clock duration. (3) **8b/10b coding** — high-speed protocols embed framing markers in the bit stream itself.

What's the maximum baud rate?

Limited by the shift register's clock-to-Q + setup time and the wire's bandwidth. UARTs typically run up to 1 Mbps; SPI to 100 Mbps; SerDes to 100+ Gbps. The shift register is rarely the bottleneck — clock recovery and signal integrity are.

How does parity work?

An extra bit appended to each byte: even parity makes the total bit-count even; odd parity makes it odd. The receiver checks that the count matches; a single-bit corruption flips the count and is detected. Multi-bit errors can be undetected.

What happens if TX and RX clocks drift?

In synchronous protocols (SPI), both sides share the same clock — drift is impossible. In asynchronous protocols (UART), the receiver re-synchronizes on each start bit, allowing small drift between bytes. Excessive drift causes bit slips and corruption.