Basic Shift Register Circuit Simulator

Interactive simulator requires JavaScript

Enable JavaScript to load the live circuit. The truth table below describes the circuit's behaviour.

Open in Full Simulator Browse All Templates

What You'll Learn

Chain flip-flops to form a shift register.
Distinguish SISO, SIPO, PISO, PIPO shift register configurations.
See bits propagate one position per clock edge.
Connect this to UART, SPI, and JTAG serial protocols.
Apply shift registers as delay lines and pseudo-random generators (LFSRs).

How It Works

A shift register is a chain of D flip-flops where each flip-flop's output feeds the next one's input. On every clock edge, every bit shifts one position. This makes the register act as a delay line, FIFO, or serial-to-parallel converter, depending on how you wire the I/O.

The basic operation: bit 0 captures the serial input; bit 1 captures bit 0's previous value; bit 2 captures bit 1's; etc. After N clock edges, an N-bit shift register has fully "flushed" the serial input through all positions.

Four common configurations: - SISO (serial-in serial-out): One serial input, one serial output (after N cycles). - SIPO (serial-in parallel-out): Serial input, parallel outputs from each flip-flop. - PISO (parallel-in serial-out): Parallel load, then shift out one bit per clock. - PIPO (parallel-in parallel-out): Just a register, no shift.

Shift registers are the basis of many serial protocols — UART, SPI, JTAG — where data is transmitted bit-by-bit on a single wire and reassembled on the receive side.

Try It Step-by-Step

Set the inputs in the embed above, then read what should happen and confirm.

1

Serial in = 1 Clock = rising

Expected: Bit 0 = 1, others shifted right

What you'll see: Serial input is captured into bit 0; bit 0's previous value moves to bit 1; etc. Each clock edge shifts the chain by one.
2

Serial in = 0 Clock = after 4 edges

Expected: After 4 zeros, register clears

What you'll see: Sustained 0 input — after N (= width) clock edges the register is fully flushed to all-zeros.
3

Serial in = 1 Clock = after 4 edges

Expected: Register fills with 1s: 1111

What you'll see: Sustained 1 input — register fills bit-by-bit until all positions are 1.
4

Serial in = alternating 1 0 1 0 Clock = running

Expected: Pattern propagates through register

What you'll see: Watch the alternating pattern shift through. After 4 cycles the register holds 1010 (or 0101 depending on phase).

Components Used

Real-World Applications

Serial communication (UART, SPI, JTAG). Transmit-side uses PISO; receive-side uses SIPO. The serial wire carries one bit per clock; the shift register reassembles bytes.

Display drivers. LED matrix and 7-segment chips often use SIPO shift registers to expand a few SPI lines into many output bits.

Pseudo-random generators. LFSRs (linear feedback shift registers) use a shift register with XOR feedback to produce pseudo-random bit sequences.

Pipeline delay lines. A shift register can introduce N cycles of delay to align signals between fast and slow paths.

Serial test patterns. Built-in self-test (BIST) uses shift registers to inject test patterns and capture results sequentially.

Frequently Asked Questions

Why are shift registers useful for serial-to-parallel conversion?

Serial buses transmit one bit per clock; the receiver needs to reassemble them into multi-bit words. A SIPO shift register collects N bits over N clocks, then presents them all in parallel — exactly the conversion needed.

What's the latency from serial input to all-bits-loaded?

N clock cycles for an N-bit shift register. After N edges, the first input bit has propagated to the last position, and the register holds N bits of data.

Can I shift left and right?

Yes — bidirectional shift registers have a direction control input. Each flip-flop's D input becomes a 2-to-1 MUX that picks the previous bit (shift left) or next bit (shift right). Bidirectional registers are common in DSP and graphics.

How is an LFSR different from a basic shift register?

An LFSR (linear-feedback shift register) feeds the output through XOR with one or more middle bits back to the serial input. The XOR creates a pseudo-random bit sequence with maximal period 2^N − 1 (for properly chosen tap positions).

What's the maximum clock speed of a shift register?

Limited by the slowest flip-flop's clock-to-Q + setup time. Modern CMOS shift registers run at multi-GHz speeds; specialty serial transceivers run faster with custom flip-flop circuits and clock recovery.