The Half Adder: Your First Step into Digital Logic Design

TL;DR: A half adder is the simplest binary-addition circuit. Two inputs (A, B) produce two outputs: Sum = $A \oplus B$ (XOR) and Carry = $A \cdot B$ (AND). It’s only “half” an adder because it can’t accept a carry-in from a previous column — that requires the full adder.

Binary arithmetic is one part of many digital systems. A half adder is a compact example because its two Boolean outputs encode $A+B$: Sum has weight 1 and Carry has weight 2. It is a useful derivation model, not a claim that every synthesized adder, arithmetic logic unit (ALU), or processor contains a literal XOR-plus-AND half-adder cell.

Defining the HALF_ADDER

A HALF_ADDER is a combinational logic circuit designed to perform the addition of two single binary digits. In the hierarchy of digital systems, it sits just above basic logic gates but below the more complex FULL_ADDER and ALU (Arithmetic Logic Unit). It’s the digital equivalent of adding two numbers in the rightmost column when you do long addition on paper.

The circuit takes two inputs, typically labeled $A$ and $B$, and produces two distinct outputs:

1. Sum ($S$): The result of the addition in the current bit position.
2. Carry ($C$): The “carry-the-one” bit that is passed to the next, more significant column in a multi-bit addition.

To understand why we need two outputs, we only need to look at the four fundamental rules of binary addition:

• $0 + 0 = 0$ (Sum = 0, Carry = 0)
• $0 + 1 = 1$ (Sum = 1, Carry = 0)
• $1 + 0 = 1$ (Sum = 1, Carry = 0)
• $1 + 1 = 10_2$ (Sum = 0, Carry = 1)

These four rows specify the half-adder function. When A and B are both 1, Carry records the higher-order bit of the two-bit result. Calling that signal “overflow” without stating a fixed result width or number format can be misleading.

Explore HALF_ADDER Behavior

The Truth Table: Revealing the Logic

A truth table exhaustively maps every stable input combination to the required logical outputs. It specifies function independently of a physical implementation.

Compare each output column with the elementary gate truth tables.

The Sum (S) column is HIGH only when the inputs are different. If both are LOW or both are HIGH, the Sum is LOW. This is the exact definition of an XOR gate: it outputs 1 when the inputs differ and 0 when they match.

The Carry (C) column is HIGH only when both inputs are HIGH. This is the unmistakable signature of an AND gate: it outputs 1 only when every input is 1.

The Boolean Expression

Boolean algebra expresses the two output functions directly.

For the Sum output, we use the XOR operator, denoted by $\oplus$:

For the Carry output, we use the AND operator, represented by a dot ($\cdot$):

The output columns match two familiar functions: XOR and AND. This gives a convenient textbook implementation. The truth table specifies behavior rather than a unique topology; a cell library, FPGA lookup table, or synthesis tool may implement an equivalent network differently.

Why is it Only “Half” an Adder?

One half adder per bit position is insufficient for a general multi-bit addition because the component has no carry-in input.

Think back to primary school math. If you’re adding $18 + 24$, you start at the right: $8 + 4 = 12$. You write down the $2$ and carry the $1$. Now, look at the next column. You aren’t just adding $1 + 2$; you’re adding $1 + 2 + \text{the carried } 1$.

That second column requires three inputs. A half adder accepts only A and B. It can implement the least-significant column when its incoming carry is known to be 0. At later columns it must be combined with additional logic—for example, two half adders plus OR—to implement a full adder.

A full-adder interface adds the third input $C_{in}$. The term “half adder” is conventional; it denotes the missing carry-in rather than a quantitative claim that the component performs exactly half of a physical adder’s work.

Building the Circuit on digisim.io

Build the textbook gate-level form in the DigiSim editor:

1. Place Inputs: Drag two INPUT_SWITCH components onto the canvas. Label them A and B.
2. Place Logic: Add one XOR gate and one AND gate.
3. Place Outputs: Add two OUTPUT_LIGHT components. Label them Sum and Carry.
4. Wiring:

• Connect Input A to the first input of the XOR and the first input of the AND.
• Connect Input B to the second input of the XOR and the second input of the AND.
• Connect the XOR output to the Sum light.
• Connect the AND output to the Carry light.

Verifying the stable function

Toggle all four stable input combinations and compare Sum and Carry with the truth table. If the selected simulator model includes propagation delay, inspect that modeled timing separately; do not infer a physical gate delay or technology from the animation.

Open Half Adder Template

Verification with the OSCILLOSCOPE

Use the waveform view to distinguish stable function from modeled transition timing.

Place an OSCILLOSCOPE_8CH into your circuit. Connect Channel 1 to Input A, Channel 2 to Input B, Channel 3 to Sum, and Channel 4 to Carry.

As you toggle the switches, the OSCILLOSCOPE shows the model’s discrete logic states over simulation time. Carry is asserted while both inputs are 1; it is not merely a spike. The digital model does not establish a 5 V electrical level unless the component documentation explicitly defines one. A physical waveform requires voltage thresholds, edge rates, loading, and an instrument model that this logic trace may omit.

XOR and AND path delays depend on the chosen implementation and load. A transition can expose an intermediate state when reconvergent paths settle at different times, but its direction and duration must come from the actual model or characterized hardware rather than an invented generic value.

Where the function appears

The half-adder function appears within several larger arithmetic structures, even when no literal component carries that name.

1. A least-significant addition stage

If an adder’s least-significant carry-in is permanently 0, its first stage has the half-adder function. Designers may still instantiate a uniform full-adder cell with Cin tied low, use a dedicated carry-chain primitive, or employ a different arithmetic structure. Area, power, and speed benefits cannot be inferred from the logical name alone.

2. Address Generation Units (AGUs)

An incrementer can be built from a chain in which each bit combines the input bit with a carry that indicates whether all lower bits rolled over. Half-adder-like equations can describe each stage, but synthesis may map the function to dedicated carry logic or another topology.

Moving Forward in the Curriculum

The following topics extend the same arithmetic specification:

• Half Adder vs. Full Adder: adding the carry-in input.
• Mastering Binary Addition: Building a 4-Bit Ripple Carry Adder: stringing adders into multi-bit arithmetic.
• Mastering Boolean Algebra: the language used to derive these expressions.

Final Thoughts

The half adder gives a complete two-input Boolean specification: XOR for Sum and AND for Carry in the textbook gate-level form.

The next post in this series, The Half Adder vs. The Full Adder, shows how to extend this circuit to accept carry-in and chain it across multiple bits. Open the HALF_ADDER component reference to verify the truth table directly.