Propagation Delay: The Physics That Dictates Digital Speed

TL;DR: Propagation delay ($t_{pd}$) is the interval between a specified input crossing and the corresponding output crossing. It depends on the device, load, input slew, voltage, temperature, process, and routing. In synchronous logic, maximum data-path delay contributes to setup timing and minimum delay contributes to hold timing; both must be checked.

Real gates and wires do not respond instantly. Their delays can range from picoseconds in short on-chip paths to nanoseconds or longer in board-level devices and heavily loaded networks. What matters is not the number of gates in the whole design, but the delay along each path between a launch point and a capture point.

Review the NOT gate component

The Anatomy of a Delay

Propagation delay is measured between defined voltage thresholds—commonly the midpoint of the input transition and the midpoint of the corresponding output transition. The exact test voltages, load, supply, and input waveform come from the device datasheet.

This delay isn’t a single, uniform value. We measure it in two distinct ways because the underlying physics of switching a transistor “on” versus “off” are different:

• $t_{pLH}$ (Low-to-High Delay): The time taken for the output to transition from a logic 0 (low) to a logic 1 (high).
• $t_{pHL}$ (High-to-Low Delay): The time taken for the output to transition from a logic 1 (high) to a logic 0 (low).

Pull-up and pull-down networks need not have identical strength, so $t_{pLH}$ and $t_{pHL}$ can differ. Transistor sizing and output loading determine which is larger; do not assume one direction from the logic function alone. An average is sometimes useful for characterization:

Worst-case digital timing usually uses the relevant maximum or minimum arc rather than this average. Unequal rising and falling delays can also contribute to duty-cycle distortion in a clock network.

Technical Specification: The NOT Gate

To understand delay, we must first understand the simplest logic element: the NOT gate. While its logic is trivial, its physical behavior is the foundation of all timing analysis.

The Boolean expression for this operation is:

A logic simulator may use ideal zero-delay gates or a simplified per-component delay. That is useful for learning event order and hazards, but it is not a substitute for a real device’s timing model, datasheet limits, or static timing analysis.

The Physical Origins: Why Instant is Impossible

Propagation delay follows from charging capacitance through finite resistance and from signal travel through interconnect. Several variables contribute at once.

1. Transistor and internal-node delay

Logic gates contain transistor networks with parasitic capacitances. Changing state requires charging and discharging internal and output nodes through finite transistor resistance. Device geometry, input slew, supply voltage, temperature, and manufacturing variation all affect the result.

2. Interconnect resistance, capacitance, and flight time

Metal interconnect has resistance and capacitance to nearby conductors. Short on-chip wires are often modeled as distributed RC networks; longer PCB traces behave as transmission lines with a finite propagation velocity. Coupling, geometry, termination, and the receiving threshold influence when the destination recognizes an edge.

3. Load capacitance and fan-out

Each driven input, package pin, probe, and length of interconnect contributes load. More capacitance generally slows the output edge and changes the propagation delay measured at the next threshold. Datasheet delay limits are valid only under their stated test conditions, so a number quoted at 15 pF or 50 pF should not be transferred blindly to a different load.

The Critical Path: Your Circuit’s Ultimate Speed Limit

In a multi-level logic path, cell and interconnect delays accumulate. Parallel branches do not all add together; timing follows each possible path from its launch point to its capture point.

This leads to the critical path: the path with the least setup slack under a particular set of constraints and operating conditions. In a simple single-clock design, it is often the longest maximum-delay register-to-register path. Real timing tools also analyze input/output paths, generated clocks, clock skew, and exceptions.

Consider the classic 4-bit ripple-carry adder, which you can build using the ADDER component in digisim.io. It’s built from four full-adder circuits chained together. The sum bit for the first stage ($S_0$) is calculated quickly. However, the carry-out bit ($C_{out}$) from this first stage is required to calculate the sum for the second stage ($S_1$). This dependency continues down the line. The final sum bit, $S_3$, cannot be calculated until the carry signal has “rippled” through all three preceding stages.

If each full-adder carry stage has a similar delay $t_{carry}$, the final carry of a 4-bit ripple design takes roughly $4t_{carry}$ plus wiring and loading effects. Extending the same topology to 64 bits makes the carry path grow approximately linearly, which motivates carry-lookahead and parallel-prefix structures.

For a simplified same-clock path with ideal clock arrival, the clock period must allow a source register to launch data, the maximum-delay path to settle, and the destination register’s setup time:

Where:

• $t_{clk-q}$ is the time it takes for a register’s output to change after a clock edge.
• $t_{pd(critical)}$ is the delay of the longest logic path between registers.
• $t_{setup}$ is the time the data must be stable at a register’s input before the next clock edge.

In that simplified model, the corresponding upper bound is:

Production static timing analysis also includes clock arrival times and uncertainty and evaluates many process, voltage, and temperature corners. A separate minimum-delay check verifies hold time; a path can pass setup and still fail hold.

Open the 4-bit binary counter template

Common Pitfall: Glitches, Hazards, and Race Conditions

When related signals travel through paths with unequal delays and later reconverge, an output can briefly take an unintended value. This is a combinational hazard. The word “race” is broader and is also used for state-dependent behavior in asynchronous or sequential circuits, so the two terms are not exact synonyms.

A common example: $Y = A \cdot \overline{A}$. Mathematically this is always 0. Built from real gates, $A$ feeds directly into an AND gate, and also feeds into a NOT gate whose output goes to the same AND gate.

When $A$ transitions from 0 to 1, the direct path to the AND gate sees the new 1 almost instantly. However, the other path must first go through the NOT gate, which introduces a propagation delay, $t_{pd(NOT)}$. For a brief moment — equal to $t_{pd(NOT)}$ — both inputs to the AND gate will be 1 (the new value of $A$ on the direct path, and the old value of $\overline{A}$ still propagating through the inverter). This causes the output $Y$ to glitch, momentarily pulsing to 1 when it should have remained at 0. (Textbooks call this a static-0 hazard: the output is supposed to stay LOW but briefly goes HIGH.)

A transient may be harmless if it settles before a downstream register’s sampling window, or harmful if it reaches an asynchronous control, clock, or other pulse-sensitive input. A waveform viewer can expose the event only when the simulator models the unequal path delays that create it.

Visualizing Delay with the Ring Oscillator

One compact demonstration of accumulated delay is a ring oscillator, but it requires either physical gates or a simulator that supports feedback with nonzero propagation delay.

A ring oscillator contains an odd number of inverting stages in a loop. In physical hardware, the stages cannot all settle consistently, and finite delay produces oscillation. Frequency depends on stage delay, loading, supply, temperature, and process—not just the gate count.

Step-by-step build

1. Check the model: Confirm that the simulator supports combinational feedback and nonzero gate delay. If it uses ideal zero-delay logic, perform this experiment with physical devices or a delay-aware HDL simulator.
2. Place the Gates: Place three NOT gates in a row.
3. Chain Them: Connect the output of the first to the input of the second, and the second to the third.
4. Close the Loop: Connect the output of the third NOT gate back to the input of the first.
5. Add Instrumentation: Connect a waveform channel to the output of the third gate.

What you’ve built is a circuit whose output is constantly chasing itself. The signal flips, propagates through the chain of inverters, and arrives back at the beginning, inverted, causing it to flip again. The time it takes to make one full oscillation is directly related to the cumulative propagation delay.

For $N$ similar stages, a first-order approximation is:

where $N$ is the number of inverters and $t_{pd}$ is the average propagation delay of a single inverter. The factor of 2 appears because a complete oscillation requires the signal to traverse the chain twice: once to transition HIGH and once to transition LOW. The oscillation frequency is therefore:

Adding two stages should lower the frequency if the other conditions remain similar. Rearranging the equation estimates an effective average stage delay, including interconnect and loading. On-chip ring oscillators are used as process, voltage, and temperature monitors, but precise cell characterization uses controlled test structures, waveforms, and statistical models rather than this one estimate alone.

Real-World Use: Taming the Delay

Managing propagation delay is a daily battle for hardware engineers. It isn’t just about making things faster; it’s about making them work at all.

CPU core design

A processor’s feasible operating points depend on timing closure across the design as well as voltage, temperature, power, and product guardbands. Engineers use static timing analysis to find paths with negative or low slack, then may change logic structure, pipeline boundaries, placement, routing, buffering, or cell sizes. There is rarely one permanently “critical” path across all modes and operating corners.

High-speed data interfaces

Parallel interfaces such as DDR manage the arrival relationship among data, strobes, clocks, commands, packages, and vias. PCB designers route signals to satisfy timing and signal-integrity budgets, sometimes adding serpentine length where needed. The goal is controlled electrical delay, not identical geometric length: package delay, layer velocity, coupling, and controller training can all affect the budget.

Mastering the Rhythm of Logic

Propagation delay connects Boolean design to physical implementation. It explains why path depth matters, why a correct truth table can still glitch during a transition, and why both maximum- and minimum-delay checks are required.

Keep the waveform viewer open while exploring timing. A displayed lag is the behavior of the simulator’s delay model; compare it with a component datasheet or implementation timing report before drawing conclusions about hardware.

Continue with setup, hold, and metastability for the constraints surrounding propagation delay, or multi-input logic gates for cascade-vs-tree depth. The NOT gate component reference provides the logical behavior used in the ring-oscillator exercise.

Engineering References

• Texas Instruments, Designing With Logic — propagation delay, output loading, and datasheet test conditions.
• AMD, Reviewing Timing Slack — setup/hold slack, skew, uncertainty, and path analysis.