Counters and State Machines: Controlling Digital Sequences

System Architect

📅 January 2026 • ⏱️ 18 min read • 🎓 Intermediate-Advanced

From binary counters to traffic light controllers, digital systems need to step through sequences of states. In this tutorial, you'll learn how counters count clock pulses and how finite state machines (FSMs) manage complex behaviors.

What is a Counter?

A counter is a sequential circuit that cycles through a sequence of states on each clock pulse. The simplest is a binary counter that counts 0, 1, 2, 3... and wraps around.

Counter Characteristics

Modulus: The number of states before wrapping (mod-8 counts 0-7)

Direction: Up-counter, down-counter, or bidirectional

Type: Synchronous (all flip-flops clocked together) or Asynchronous (ripple)

A 4-bit binary counter: on each clock pulse, it increments from 0000 to 1111, then wraps to 0000.

Building a 4-Bit Ripple Counter

The simplest counter is a ripple counter: chain T flip-flops (in toggle mode) where each flip-flop's output clocks the next.

A ripple counter: Q0 toggles every clock, Q1 every other clock, Q2 every fourth, etc.

Key Insight: Ripple Delay

In a ripple counter, each stage waits for the previous to toggle before it can respond. This creates a "ripple" delay that accumulates. For high-speed applications, synchronous counters (all stages clocked simultaneously) are preferred.

What is a Finite State Machine?

A Finite State Machine (FSM) is a circuit that can be in one of a finite number of states and transitions between states based on inputs and clock edges. FSMs control:

• Traffic light sequences
• Vending machine logic
• Communication protocols
• CPU control units
• Game logic and AI

A traffic light FSM: states cycle through Green→Yellow→Red, controlled by timing logic.

FSM Components

FSM Architecture

State Register: Flip-flops that store the current state

Next State Logic: Combinational circuit determining the next state

Output Logic: Combinational circuit generating outputs based on state (and possibly inputs)

Moore vs. Mealy Machines

Moore Machine

Outputs depend ONLY on the current state.

Example: Traffic light—being in "GREEN" state means green light is on, regardless of inputs.

Mealy Machine

Outputs depend on both the current state AND inputs.

Example: Sequence detector—output depends on state AND the current input bit.

A 4-state finite state machine with state transitions controlled by input signals.

Designing an FSM

1. Draw the state diagram: Circles for states, arrows for transitions
2. Assign binary codes to states: e.g., Green=00, Yellow=01, Red=10
3. Derive the transition table: Current state + inputs → Next state
4. Derive flip-flop inputs: Use D flip-flop: D = Next State
5. Derive output logic: State → Output signals
6. Build the circuit

Applications

🚦 Traffic Light Controller

States: Green NS, Yellow NS, Red NS (Green EW), Yellow EW. Timer-based transitions ensure safe intersection timing.

🎰 Vending Machine

States tracking total money inserted. Transitions on coin insertions. Output dispenses product when threshold reached.

🔢 Sequence Detector

States remembering recent inputs. Outputs HIGH when target sequence (e.g., 1011) is detected in serial input stream.

🖥️ CPU Control Unit

States for each phase of instruction execution: Fetch, Decode, Execute, Memory, Writeback.

Try It Yourself!

1. Build a 3-bit counter: Counts 0-7 and wraps
2. Mod-6 counter: Counts 0-5 (add reset logic at 6)
3. Traffic light FSM: 3 states with timed transitions
4. Sequence detector: Detect the pattern "101" in a bit stream

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