Multiplexers (MUX) Demystified: The Data Traffic Controller

TL;DR: A multiplexer selects one of $2^n$ data inputs with an $n$-bit select code. For a 4-to-1 MUX, $Y=\overline{S_1}\overline{S_0}D_0+\overline{S_1}S_0D_1+S_1\overline{S_0}D_2+S_1S_0D_3$. Constants on the data inputs turn a MUX into a truth-table implementation, while real FPGA LUTs combine stored configuration with architecture-specific selection circuitry.

Multiplexers select operand sources in processors, responses in interconnects, and configured signals in programmable logic. Analog and video switches solve a related routing problem but have electrical behavior beyond a one-bit digital MUX. This guide covers the Boolean foundation, gate-level construction, cascading, and function-generation property.

What is a Multiplexer?

A multiplexer is a combinational circuit that selects one of several data inputs and forwards it to a single output line. The selection is controlled by a separate set of select lines that encode a binary address corresponding to the desired input.

For a fully populated power-of-two MUX:

$n$ select lines can choose from $2^n$ data inputs.

One select line addresses two inputs, two address four, and three address eight. Non-power-of-two interfaces can leave codes unused or define a default path, and many practical devices also include an enable or strobe.

A 4-to-1 multiplexer: 2 select lines choose between 4 inputs. The selected input appears at the output.

The 2-to-1 MUX: The Simplest Data Selector

The 2-to-1 MUX is the fundamental building block. It has 2 data inputs ($D_0$, $D_1$), 1 select line ($S$), and 1 output ($Y$).

The Boolean expression is straightforward. We need $D_0$ to pass through when $S=0$ and $D_1$ to pass through when $S=1$:

$Y = \overline{S} \cdot D_0 + S \cdot D_1$

One canonical basic-gate implementation uses:

• One NOT gate to produce $\overline{S}$
• Two AND gates: one computes $\overline{S} \cdot D_0$, the other computes $S \cdot D_1$
• One OR gate to combine both AND outputs into the final result

A 2-to-1 MUX built from AND, OR, and NOT gates. When S=0, $D_0$ passes through; when S=1, $D_1$ passes through.

The 4-to-1 MUX: Boolean Expression and Gate-Level Design

A 4-to-1 MUX has 4 data inputs ($D_0$ through $D_3$) and 2 select lines ($S_1$, $S_0$). The select lines form a 2-bit binary address that chooses which input reaches the output.

Each row of this table corresponds to one product term where the select lines “enable” exactly one data input. The complete Boolean expression for the 4-to-1 MUX is:

$Y = \overline{S_1}\,\overline{S_0}\,D_0 + \overline{S_1}\,S_0\,D_1 + S_1\,\overline{S_0}\,D_2 + S_1\,S_0\,D_3$

This expression tells us exactly what hardware we need:

• 2 NOT gates to produce $\overline{S_1}$ and $\overline{S_0}$
• 4 three-input AND gates, each gating one data input with the appropriate select combination
• 1 four-input OR gate to combine all four AND outputs

The direct Boolean drawing contains two inversions, four product terms, and an OR reduction. “Seven gates” assumes arbitrary three- and four-input gates count as one each; a physical library or FPGA may map the function differently.

4-to-1 MUX with function table and scaling pattern. $n$ select lines choose from $2^n$ inputs.

Building a 4-to-1 MUX on digisim.io

Follow these steps to build a 4-to-1 MUX from discrete gates:

1. Place the select lines. Drag two INPUT_SWITCH components onto the canvas and label them $S_1$ and $S_0$.
2. Generate the complements. Place two NOT gates. Connect $S_1$ to one and $S_0$ to the other, producing $\overline{S_1}$ and $\overline{S_0}$.
3. Place the data inputs. Add four INPUT_SWITCH components and label them $D_0$, $D_1$, $D_2$, and $D_3$.
4. Create the AND array. Place four AND gates (3-input each):
   • AND-0: inputs are $\overline{S_1}$, $\overline{S_0}$, and $D_0$
   • AND-1: inputs are $\overline{S_1}$, $S_0$, and $D_1$
   • AND-2: inputs are $S_1$, $\overline{S_0}$, and $D_2$
   • AND-3: inputs are $S_1$, $S_0$, and $D_3$
5. Combine the results. Place one OR gate and connect all four AND outputs to it. The OR output is your final output $Y$.
6. Add visualization. Connect $Y$ to an OUTPUT_LIGHT.

Toggle the select switches to route different data inputs to the output. In a stable valid select state, only the selected product term is enabled; its data value determines Y.

Cascading MUXes: Building an 8-to-1 from 4-to-1 Units

One of the most powerful properties of multiplexers is that they can be cascaded to handle more inputs. You do not need to design an 8-to-1 MUX from scratch; you can build it from smaller units.

An 8-to-1 MUX requires 3 select lines ($S_2$, $S_1$, $S_0$) and 8 data inputs ($D_0$ through $D_7$). Here is how to construct it from two 4-to-1 MUXes and one 2-to-1 MUX:

1. First stage (two 4-to-1 MUXes):
   • MUX-A handles $D_0$-$D_3$, with $S_1$ and $S_0$ as its select lines.
   • MUX-B handles $D_4$-$D_7$, with $S_1$ and $S_0$ as its select lines.
2. Second stage (one 2-to-1 MUX):
   • The output of MUX-A connects to $D_0$ of the final MUX.
   • The output of MUX-B connects to $D_1$ of the final MUX.
   • $S_2$ serves as the select line for this final MUX.

When $S_2 = 0$, the final MUX passes the result from MUX-A (inputs $D_0$-$D_3$). When $S_2 = 1$, it passes the result from MUX-B (inputs $D_4$-$D_7$). The lower select lines $S_1$ and $S_0$ determine which of the four inputs within the selected group reaches the output.

This hierarchical approach scales to any size. A 16-to-1 MUX can be built from two 8-to-1 MUXes and one 2-to-1, or from four 4-to-1 MUXes feeding a second-level 4-to-1 MUX.

An 8-to-1 MUX with 3 select lines. This can be built from two 4-to-1 MUXes and one 2-to-1 MUX.

The MUX as a Universal Function Generator

A $2^n$-to-1 MUX can implement any Boolean function of n variables by connecting those variables to the select lines and wiring the data inputs to constants from the truth table. The MUX is itself logic, so this is a structural implementation—not logic “for free.”

For example, consider a 3-variable function $F(A, B, C)$. Using an 8-to-1 MUX:

1. Connect $A$, $B$, and $C$ to the select lines $S_2$, $S_1$, and $S_0$.
2. For each row of the truth table, the select combination addresses one data input. Wire that data input to 1 if $F=1$ for that row, or to 0 if $F=0$.

The MUX output then reproduces the truth table. FPGA lookup tables use stored configuration bits and selection circuitry to provide the same externally visible capability: any function that fits the LUT input count. The internal structure and dedicated cascade resources are device-family-specific.

You can also use a smaller MUX by applying one input variable to the data lines instead of the select lines. For instance, a 3-variable function can be implemented with a 4-to-1 MUX (using only 2 select lines) by connecting $A$ and $B$ to the select lines and wiring each data input to 0, 1, $C$, or $\overline{C}$ as needed.

Worked Example: Implementing a Majority Function

The 3-input majority function outputs 1 when two or more inputs are 1. Its truth table is:

Using an 8-to-1 MUX: Connect $A$, $B$, $C$ to $S_2$, $S_1$, $S_0$. Wire data inputs $D_0$ through $D_7$ to match the F column: $D_0=0$, $D_1=0$, $D_2=0$, $D_3=1$, $D_4=0$, $D_5=1$, $D_6=1$, $D_7=1$. No external data-function gates are needed beyond the MUX and constant sources.

Using a 4-to-1 MUX (reduced form): Connect $A$ and $B$ to $S_1$ and $S_0$. Group the truth table rows by $AB$:

• $AB=00$: $F=0$ for both $C=0$ and $C=1$. Wire $D_0 = 0$.
• $AB=01$: $F=0$ when $C=0$, $F=1$ when $C=1$. Wire $D_1 = C$.
• $AB=10$: $F=0$ when $C=0$, $F=1$ when $C=1$. Wire $D_2 = C$.
• $AB=11$: $F=1$ for both $C=0$ and $C=1$. Wire $D_3 = 1$.

This implements the same function using a smaller MUX, with $C$ connected directly to two data inputs.

Propagation Delay and Timing Considerations

Like all physical combinational circuits, a MUX has propagation delay. In the direct sum-of-products drawing, a select transition may pass through an inverter, a product term, and the OR reduction:

That is only a topology estimate. Actual delay includes cell choice, input slew, load, routing, voltage, temperature, and whether the selected path begins at a data or select input. Cascaded selection adds logical levels, but a physically wide one-level expression can also be slow because of fan-in and wiring. Use target-device timing analysis rather than assuming one topology is twice as fast as another.

Select transitions can also create a temporary output pulse if old and new data inputs differ and internal paths settle at different times. Register the result when it crosses a synchronous boundary, keep select stable for the required interval, and avoid using an unqualified MUX output as a clock or asynchronous write strobe. Functional simulation validates selection logic but may not model physical hazards or delay.

The General Boolean Expression for an $N$-to-1 MUX

We can generalize the MUX Boolean expression to any size. For a $2^n$-to-1 MUX with select lines $S_{n-1}, S_{n-2}, \ldots, S_0$ and data inputs $D_0, D_1, \ldots, D_{2^n - 1}$:

$Y = \sum_{i=0}^{2^n - 1} \left( D_i \cdot m_i \right)$

where $m_i$ is the $i$-th minterm of the select variables. Each minterm is a product of all select variables, each appearing in either true or complemented form depending on the binary representation of $i$. For instance, in an 8-to-1 MUX, the minterm for $i=5$ (binary 101) is $S_2 \cdot \overline{S_1} \cdot S_0$.

This formulation makes it clear that a MUX is literally a hardware implementation of the sum-of-minterms canonical form. Every Boolean function has a unique sum-of-minterms expression, and a MUX can implement it directly by wiring the data inputs to the appropriate constant values.

The Enable Input

Many commercial MUX ICs include an enable or strobe pin, often active-low. Disabled behavior is part-specific: an output may be forced low, forced high, or—in a different device class—placed in high impedance. For an abstract active-high enable E that forces Y low when disabled:

$Y = E \cdot \left(\overline{S_1}\,\overline{S_0}\,D_0 + \overline{S_1}\,S_0\,D_1 + S_1\,\overline{S_0}\,D_2 + S_1\,S_0\,D_3\right)$

An enable can simplify cascading and control qualification, but it is not required for every MUX hierarchy. A push-pull MUX output must not be mistaken for a tri-state bus driver.

When building cascaded MUXes on digisim.io, you can simulate the enable function by adding an AND gate between the final OR output and an enable switch.

Real-World Analogy: TV Channel Selector

Imagine you have 4 video sources (gaming console, cable box, Blu-ray, streaming stick) and one TV. A MUX is like the input selector: the remote’s button (select lines) determines which source appears on screen (output). The video data flows continuously from all four sources, but the MUX gates only the selected one through to the display.

TV channel selector as a MUX: select lines choose which input source appears on the TV.

The Demultiplexer (DEMUX)

The opposite of a MUX is a Demultiplexer (DEMUX). While a MUX selects one of many inputs and routes it to a single output, a DEMUX takes a single input and routes it to one of many outputs based on the select lines.

The Boolean expressions for a 1-to-4 DEMUX are:

$Y_0 = D \cdot \overline{S_1} \cdot \overline{S_0}$ $Y_1 = D \cdot \overline{S_1} \cdot S_0$ $Y_2 = D \cdot S_1 \cdot \overline{S_0}$ $Y_3 = D \cdot S_1 \cdot S_0$

Notice that a DEMUX is structurally identical to a decoder with an enable input. When the data input $D$ acts as the enable, the “address” on the select lines determines which output receives the signal.

A 1-to-4 DEMUX: one input is routed to one of four outputs based on 2 select lines.

Applications of Multiplexers

Multiplexers appear at every level of digital system design. Here are the most important applications, with enough detail to understand why MUXes are indispensable.

CPU Register File

In a small register bank built from discrete flip-flops, each asynchronous read port can be modeled as a word-wide MUX selected by a register index. An eight-register, eight-bit teaching bank would use eight parallel 8-to-1 bit selections per read port. Physical ASIC and FPGA register files may instead use memory macros, decoded word lines, bit lines, dedicated RAM resources, or distributed logic. The MUX model describes the externally visible selection, not one mandatory transistor topology.

ALU Input Selection

The ALU’s operands do not always come from registers. Sometimes an operand is an immediate constant embedded in the instruction, or a value read from memory. A MUX at each ALU input allows the control unit to select the operand source: register file output, immediate value, or memory data register. This single MUX per ALU input gives the CPU the flexibility to execute register-register, register-immediate, and memory-register instructions using the same ALU hardware.

Memory Address Decoding and Bus Arbitration

When multiple targets can return data, a MUX can select the response associated with a decoded request. When several masters request a resource, an arbiter chooses ownership and routing MUXes forward the selected master’s address, data, and controls. The MUX does not implement fairness or the request/grant handshake; it only routes according to the arbitration result.

FPGA Lookup Tables

A common FPGA logic primitive is a lookup table (LUT). Configuration state stores truth-table values, and the logic inputs select the applicable value. A conceptual k-input LUT therefore behaves like a $2^k$-entry truth table selected by k inputs. Actual FPGA families use architecture-specific LUT circuits, fracturing modes, dedicated cascade multiplexers, and routing, so “a 64-to-1 MUX” is a useful functional model rather than a universal physical schematic.

Try It Yourself

Build these circuits in the digisim.io editor to solidify your understanding:

1. Build a 2-to-1 MUX from 2 AND gates, 1 OR gate, and 1 NOT gate. Verify all four input combinations.
2. Expand to a 4-to-1 MUX using the Boolean expression above. Probe the output as you sweep through stable select combinations.
3. Cascade two 4-to-1 MUXes and a 2-to-1 MUX to build an 8-to-1. Verify that all 8 inputs are individually addressable.
4. Implement a Boolean function using a MUX. Pick any 3-variable function from a truth table and program it into an 8-to-1 MUX by hardwiring the data inputs.
5. Build a DEMUX to reverse the routing: send one signal to one of four outputs.

Continue with decoders and encoders (the structural cousin of the DEMUX), see how MUXes feed the ALU in the fetch-decode-execute cycle, or open the AND gate component reference — the primary building block of every MUX.

Reference

• Texas Instruments SN74HC151 8-to-1 data selector/multiplexer product documentation