Decoders and Encoders: Driving a 7-Segment Display

TL;DR: An enabled active-high binary decoder maps an $n$-bit code to one of $2^n$ asserted outputs; active-low variants invert that convention. A plain encoder assumes a one-hot input, while a priority encoder defines a winner for many-hot input. A BCD-to-seven-segment block is a code converter—not a one-hot decoder—because several segment outputs can be active together.

Decoders and encoders translate between compact binary indices and wider signal sets. They appear in address selection, instruction control, event encoding, display logic, and many other interfaces. Their names describe logical direction, but a complete interface also needs polarity, enable behavior, and a policy for invalid or simultaneous inputs.

In this guide, we will build a working BCD-to-7-segment display driver from Boolean expressions, understand the difference between common anode and common cathode displays, explore priority encoders and their role in interrupt handling, and construct these circuits on digisim.io.

What is a Decoder?

A binary decoder is a combinational circuit that maps an $n$-bit input to one selected output among as many as $2^n$. In the active-high example below, the selected output is HIGH and the rest are LOW. Real decoder ICs often provide enables and may use active-low outputs, in which case the selected line is LOW.

A 2-to-4 decoder: the 2-bit input selects which of 4 outputs is HIGH. Input 10 (binary 2) activates output $Y_2$.

The 2-to-4 Decoder: Truth Table and Boolean Expressions

Each output is a unique AND combination of the input variables (complemented or not):

$Y_0 = \overline{A_1} \cdot \overline{A_0}$ $Y_1 = \overline{A_1} \cdot A_0$ $Y_2 = A_1 \cdot \overline{A_0}$ $Y_3 = A_1 \cdot A_0$

The canonical sum-of-products drawing uses two inversions and four two-input AND terms. A synthesized ASIC or FPGA may map the same function into different cells or lookup tables.

Scaling to Larger Decoders

A 3-to-8 decoder follows the same Boolean pattern with eight minterms. In general, a direct sum-of-products form has one minterm per output. That is a teaching construction, not a universal physical gate-count requirement; larger decoders are commonly hierarchical.

The 7-Segment Display

A 7-segment display shows decimal digits using seven LED segments arranged in a figure-8 pattern. Each segment is labeled a through g:

 ━━━━━ (a)
│     │
(f)   (b)
│     │
 ━━━━━ (g)
│     │
(e)   (c)
│     │
 ━━━━━ (d)

To display any digit from 0 to 9, we selectively illuminate the appropriate combination of segments. For instance, the digit “7” requires segments a, b, and c to be on while d, e, f, and g remain off.

Common Cathode vs. Common Anode

There are two physical configurations for 7-segment displays, and the distinction matters when designing the driver circuit:

• Common Cathode: All segment LEDs share a common ground (cathode) connection. A segment lights up when its anode is driven HIGH. In this configuration, the decoder outputs are active-HIGH: a logic 1 turns a segment on.
• Common Anode: All segment LEDs share a common positive supply (anode) connection. A segment lights up when its cathode is pulled LOW. In this configuration, the decoder outputs must be active-LOW: a logic 0 turns a segment on.

DigiSim’s logical seven-segment component uses active-high segment commands. For a physical display, output polarity is only one part of the interface: provide current limiting, confirm whether the driver can source or sink the required current, and observe per-segment and package power limits.

Key Insight: This is NOT a Simple Decoder

A 7-segment decoder is fundamentally different from a standard binary decoder. A 4-to-16 decoder activates exactly ONE output at a time. A 7-segment decoder activates MULTIPLE segments simultaneously (the digit “8” lights all 7 segments). It is a combinational logic circuit with 7 independent output functions, each derived from the same 4-bit BCD input.

BCD-to-7-Segment: Truth Table

BCD (Binary Coded Decimal) uses 4 bits to represent the digits 0 through 9. The decoder maps each digit to the appropriate segment pattern:

BCD values 10 through 15 are outside the decimal-digit code. Their display patterns are design-specific: define blank, an error glyph, hexadecimal A–F, or don’t-care behavior according to the system contract.

Deriving Boolean Expressions for Segment Outputs

Each of the seven segments has its own Boolean function of the four BCD inputs $D$, $C$, $B$, $A$. To derive these expressions, we look at which digits illuminate each segment and write the sum-of-products (or use Karnaugh maps for minimization).

Segment a (top horizontal)

Segment a is ON for digits 0, 2, 3, 5, 6, 7, 8, 9 and OFF for digits 1 and 4. Listing the minterms where $a=1$:

$a = \overline{D}\,\overline{C}\,\overline{B}\,\overline{A} + \overline{D}\,\overline{C}\,B\,\overline{A} + \overline{D}\,\overline{C}\,B\,A + \overline{D}\,C\,\overline{B}\,A + \overline{D}\,C\,B\,\overline{A} + \overline{D}\,C\,B\,A + D\,\overline{C}\,\overline{B}\,\overline{A} + D\,\overline{C}\,\overline{B}\,A$

After minimization using a Karnaugh map (treating BCD inputs 10-15 as don’t-cares), this simplifies to:

$a = D + B + (A \cdot C) + (\overline{A} \cdot \overline{C})$

Or equivalently: $a = D + B + \overline{A \oplus C}$ (the XNOR of $A$ and $C$).

Segment g (middle horizontal)

Segment g is ON for digits 2, 3, 4, 5, 6, 8, 9 and OFF for digits 0, 1, 7. The minimized expression is:

$g = D + (B \oplus C) + (B \cdot \overline{A})$

Or expanded: $g = D + (B \cdot \overline{C}) + (\overline{B} \cdot C) + (B \cdot \overline{A})$.

Segment d (bottom horizontal)

Segment d is ON for digits 0, 2, 3, 5, 6, 8, 9 and OFF for digits 1, 4, 7. The minimized expression is:

$d = D + (\overline{C} \cdot \overline{A}) + (\overline{C} \cdot B) + (B \cdot \overline{A}) + (C \cdot \overline{B} \cdot A)$

The remaining four segments (b, c, e, f) follow the same process: list the minterms, decide the invalid-input policy, plot the result on a Karnaugh map, and extract a minimized expression. Commercial 74x47/48-family drivers implement specified BCD-to-segment behavior, but their internal networks need not match these particular equations.

Handling Invalid BCD Inputs

BCD only uses input values 0 through 9, but a 4-bit input can represent values 10 through 15. What should the display show for these invalid inputs? There are three common approaches:

1. Blank the display: All segments off. This provides a defined result but can hide an upstream fault unless another diagnostic reports it.
2. Don’t-care treatment: Treat inputs 10–15 as optimization freedoms. This can simplify logic, but the resulting patterns are not specified and are acceptable only when those inputs cannot matter at the display.
3. Display hex digits: For hexadecimal displays, inputs 10-15 map to letters A through F, requiring additional segment patterns.

The expressions above use the don’t-care approach. The dedicated BCD-to-seven-segment guide derives all seven functions and explains when that assumption is safe.

Building a 7-Segment Driver on digisim.io

Follow these steps to build a working display driver:

1. Place the BCD inputs. Add four INPUT_SWITCH components and label them $D$, $C$, $B$, and $A$.
2. Generate complements. Place four NOT gates to produce $\overline{D}$, $\overline{C}$, $\overline{B}$, and $\overline{A}$.
3. Build the segment logic. For each segment (a through g), implement its Boolean expression using AND and OR gates. Start with segment a using the minimized expression above.
4. Connect to the display. Place a SEVEN_SEGMENT_DISPLAY component and wire each segment output to the corresponding segment input on the display.
5. Test systematically. Toggle the input switches through all BCD values 0000 to 1001 and verify that the correct digit appears for each input.

For a shortcut, use the DIGIT_DISPLAY component. For the gate-level exercise, test all ten valid digits and all six invalid codes rather than stopping after one visible example.

What is an Encoder?

An encoder performs the inverse operation of a decoder. It takes $2^n$ input lines (of which at most one should be active) and produces an $n$-bit binary code identifying which input is active.

Simple 4-to-2 Encoder

A basic 4-to-2 encoder has 4 inputs ($D_3$, $D_2$, $D_1$, $D_0$) and 2 outputs ($Y_1$, $Y_0$). The Boolean expressions are:

$Y_1 = D_2 + D_3$ $Y_0 = D_1 + D_3$

This works correctly only if exactly one input is active at a time. If multiple inputs are active simultaneously, the output becomes ambiguous.

Priority Encoders

In real systems, multiple inputs can be active simultaneously. A priority encoder resolves this ambiguity by encoding only the highest-priority active input (typically the one with the highest index).

The X entries mean “don’t care.” Lower-priority inputs are ignored whenever a higher-priority input is active. The Valid output indicates whether any input is active at all, which is important for downstream logic that needs to distinguish “input 0 is active” from “no input is active.”

Priority Encoder in Interrupt Handling

One of the most important applications of priority encoders is in interrupt controllers. In a microprocessor system, multiple hardware devices (keyboard, network card, timer, disk drive) can request the CPU’s attention simultaneously by asserting interrupt request lines.

A priority encoder can identify the highest-ranked eligible request and produce its index. A complete interrupt controller additionally records pending events, applies masks and priority state, delivers a protocol-defined interrupt identifier or vector, tracks service, and preserves requests that were not selected. A stateless encoder alone cannot hold lower-priority requests pending.

The Intel 8259A is a historical example of a controller that combines request, mask, in-service, priority-resolution, and vector-generation behavior. Reducing the whole device to an eight-input encoder misses those stateful functions.

Building a 3-to-8 Decoder on digisim.io

Here is a step-by-step guide to building a complete 3-to-8 decoder:

1. Place the inputs. Add three INPUT_SWITCH components labeled $A_2$, $A_1$, and $A_0$.
2. Generate complements. Place three NOT gates for $\overline{A_2}$, $\overline{A_1}$, and $\overline{A_0}$.
3. Build the AND array. Place eight 3-input AND gates. Each gate receives a unique combination of original and complemented inputs:
   • $Y_0 = \overline{A_2} \cdot \overline{A_1} \cdot \overline{A_0}$
   • $Y_1 = \overline{A_2} \cdot \overline{A_1} \cdot A_0$
   • $Y_2 = \overline{A_2} \cdot A_1 \cdot \overline{A_0}$
   • …continuing through…
   • $Y_7 = A_2 \cdot A_1 \cdot A_0$
4. Add outputs. Connect each AND output to an OUTPUT_LIGHT. As you toggle the inputs, exactly one light should be on at any time.
5. Add an enable line (optional). AND each output with an enable signal to create an enabled decoder, which can be used for memory address decoding.

Applications

Memory Address Decoding

In processor systems, decoders help select which memory or I/O target responds to an address. A 2-to-4 decoder connected to two upper address bits can divide a space into four equal power-of-two regions. Additional address bits and access qualifiers are needed for other maps. If targets share a tri-state bus, bus-control logic must ensure that at most one output is enabled; many modern on-chip interconnects use multiplexed responses instead of internal tri-state wiring.

Keyboard Encoding

A scanned key matrix produces row/column observations. A priority encoder can intentionally reduce several active column lines to one index, but it loses the other simultaneous keys. Designs that need multi-key rollover preserve and process the full matrix state. Electrical ghosting, contact debounce, scan-code generation, and priority are separate concerns.

Display Systems

BCD-to-seven-segment conversion appears in clocks, meters, appliances, and scoreboards. In a multiplexed display, several digit positions can share segment drive. The controller presents one pattern and enables its matching digit, then advances. Choose complete-frame and per-digit refresh rates from flicker, camera, brightness, duty-cycle, and device limits; there is no universal 1 kHz threshold. Insert blanking if driver and digit-select delays would otherwise create ghost segments.

Instruction Decoding in CPUs

In a small teaching CPU, a 4-bit opcode can feed a 4-to-16 decoder whose selected line contributes to ALU, register, and memory controls during the fetch-decode-execute cycle. Real instruction decoding may be hierarchical, table-driven, microcoded, or distributed, and control signals normally combine opcode information with timing state and other instruction fields.

Timing and Hazards

Combinational outputs do not change simultaneously. When several input bits change, a minterm decoder can briefly select the old output, no output, or—in physical hardware—an unintended output because complemented and non-complemented paths have different delays. A seven-segment network can momentarily display a transition pattern.

Use registered inputs or outputs when the consumer samples synchronously. For a multiplexed display, blank during digit/pattern switching if ghosting matters. For chip selects and write enables, analyze hazards and meet the target device’s timing requirements rather than relying on a static truth table alone.

Try It Yourself

1. Build a 2-to-4 decoder using four AND terms with appropriate inversions. Verify that exactly one output is HIGH for each enabled input combination and none are high while disabled.
2. Wire a 7-segment display by implementing the Boolean expressions for at least segments a and g from scratch, then connect the outputs to a SEVEN_SEGMENT_DISPLAY.
3. Create a 4-to-2 encoder that encodes which of 4 buttons is pressed into a 2-bit binary code.
4. Add priority logic to your encoder so that when two buttons are pressed simultaneously, the higher-numbered button wins.
5. Build a complete BCD counter with display by connecting a COUNTER to your 7-segment decoder and watching it count 0 through 9 automatically.

Continue with counters and state machines to feed the decoder a counting input, or open the AND gate component reference — the primary building block for every decoder output. Multiplexers solve the inverse routing problem; see the multiplexer guide.

References

• Texas Instruments SN74LS47-family BCD-to-seven-segment decoder/driver data sheet
• Texas Instruments SN74HC148 priority encoder product documentation