Product of Sums (POS): Boolean Form for Efficient Logic

TL;DR: Canonical Product of Sums ANDs one maxterm for each zero row; canonical Sum of Products ORs one minterm for each one row. Counting zero rows predicts canonical term count, not the best minimized circuit. Compare minimized SOP and POS after mapping both to the target technology.

The Sum of Products (SOP) form is the natural starting point for most designers: you look at the 1s in a truth table, write minterms, and OR them together. But SOP is only half the story. Its algebraic dual, the Product of Sums (POS), approaches the same problem from the opposite direction — looking at the 0s instead of the 1s.

When a truth table has fewer zeros than ones, its canonical POS has fewer clauses than its canonical SOP has minterms. Minimization can change that comparison, and fewer written terms do not automatically mean less area, delay, or power after synthesis. POS maps naturally to OR-AND or NOR-NOR structure; SOP maps naturally to AND-OR or NAND-NAND.

Deconstructing the Product of Sums

At its core, a Product of Sums (POS) expression is exactly what the name implies: a logical product (AND) of one or more sum (OR) terms.

Consider the general form:

In this expression, each term within the parentheses—like $(A + B)$—is a “sum term.” These individual sum terms are then “multiplied” (logically ANDed) together to produce the final output, $Y$.

This structure maps naturally to a two-level OR-AND circuit. The first level consists of OR gates that create the sum terms, and their outputs feed into a single AND gate for the final product.

The fundamental building block of a canonical POS expression is the maxterm. A maxterm is a sum term that contains every variable in the function, in either its true or complemented form. While a minterm (SOP) represents a single ‘1’ in a truth table, a maxterm represents a single ‘0’.

Explore the OR Gate Component

The Maxterm Convention: The Critical pitfall

This is where most learners trip up. When transitioning from SOP to POS, the convention for what each bit means in a truth table flips entirely.

In the SOP (minterm) convention:

• A ‘1’ means the variable is in its true form ($A$).
• A ‘0’ means the variable is complemented ($\overline{A}$).

In the POS (maxterm) convention, it is the exact opposite:

• A ‘0’ means the variable is in its true form ($A$).
• A ‘1’ means the variable is complemented ($\overline{A}$).

Why this inversion? It feels counter-intuitive until you realize the goal. A canonical POS expression is built from the rows where the function’s output is 0. The objective of each maxterm is to produce a ‘0’ for its specific input combination, and only that combination.

Let’s take a 3-variable maxterm, $M_5$, which corresponds to the binary input $101$ ($A=1, B=0, C=1$). For this maxterm to evaluate to $0$, we need to construct a sum where every literal evaluates to $0$ for that specific input.

• For $A=1$, we must use its complement, $\overline{A}$, which is $0$.
• For $B=0$, we must use its true form, $B$, which is $0$.
• For $C=1$, we must use its complement, $\overline{C}$, which is $0$.

The resulting maxterm is $M_5 = \overline{A} + B + \overline{C}$. When the input is $101$, this evaluates to $0 + 0 + 0 = 0$. For any other input combination, at least one of the literals will be $1$, making the entire maxterm $1$. This is the “Aha!” moment: the AND gate at the end of a POS circuit only outputs a $0$ if at least one of its OR-gate inputs drops to $0$.

From Truth Table to POS Expression

The process of deriving a POS expression is systematic. Let’s look at a practical example. Suppose we have a logic function $Y$ defined by the following truth table:

Step 1: Identify the Zeros

Scan the truth table and find every input combination where the output $Y$ is $0$. With 000 numbered as index 0, the input indices (and maxterm numbers) are 1, 4, and 6; they are the second, fifth, and seventh displayed rows.

Step 2: Write the Maxterm for Each Zero

Apply the maxterm convention (0 = true, 1 = complement):

• Index 1 (001): $A=0, B=0, C=1 \rightarrow (A + B + \overline{C})$
• Index 4 (100): $A=1, B=0, C=0 \rightarrow (\overline{A} + B + C)$
• Index 6 (110): $A=1, B=1, C=0 \rightarrow (\overline{A} + \overline{B} + C)$

Step 3: AND the Maxterms

The final POS expression is the logical product:

This is often written in compact Pi ($\Pi$) notation:

The canonical comparison is three maxterms versus five minterms. That is not yet the best implementation. Rows 4 (100) and 6 (110) differ only in B, so their zero cells can be grouped:

This minimized POS has two clauses. A minimized SOP for the same function needs a different cover. Compare the minimized forms, then map them into actual cells or LUTs before claiming an area, delay, or power advantage.

Implementing POS on digisim.io

The OR-AND structure of POS is straightforward to build on the digisim.io canvas. The same canonical form ideas appear in our Sum of Products guide and in Karnaugh map minimization.

The Build Guide

1. Inputs: Place three INPUT_SWITCH components for $A$, $B$, and $C$.
2. Inversion: Use NOT gates to create the complements $\overline{A}$, $\overline{B}$, and $\overline{C}$.
3. The OR Level: For our expression $Y = \prod M(1, 4, 6)$, drag three OR gates onto the canvas.

• Wire the first OR to $A$, $B$, and $\overline{C}$.
• Wire the second OR to $\overline{A}$, $B$, and $C$.
• Wire the third OR to $\overline{A}$, $\overline{B}$, and $C$.

4. The AND Level: Drag one 3-input AND gate onto the canvas.
5. Final Connection: Connect the outputs of your three OR gates to the inputs of the AND gate. Attach an OUTPUT_LIGHT to the final AND output.
6. Minimize: Build $(A+B+\overline C)(\overline A+C)$ beside the canonical circuit and verify all eight rows match.

Open Universal Logic Template

Verification with the Oscilloscope

To inspect the timing of a POS circuit, use the OSCILLOSCOPE_8CH. Connect the first three channels to your inputs ($A, B, C$) and the fourth channel to the final output $Y$.

As you toggle the switches, Y is low for 001, 100, and 110. Record all eight input/output pairs rather than relying on the visual impression that POS “filters forbidden states”; these are simply the zero rows of this specified function.

Common Pitfall: Floating Inputs and Propagation Delay

When building POS circuits, beginners often forget that an AND gate with a floating input might behave unpredictably. In digisim.io, ensure all inputs are tied to a CONSTANT or an INPUT_SWITCH.

In a conceptual two-level POS circuit, a data path crosses an OR level and an AND level, plus any required input inversion. Physical timing also includes cell delay, fan-in, routing, load, input slew, and output requirements. A mapped SOP, POS, factored, or LUT implementation may win depending on the target. Use timing analysis rather than summing one generic OR and AND delay.

Real-World Applications: Where POS Shines

Why bother with POS when SOP is “easier”? Because in the real world, we often define systems by their failures or exceptions.

1. Address and Eligibility Logic

Address-selection functions can be expressed from matching regions or excluded regions. POS is convenient when a small number of zero conditions combine cleanly; prefix comparisons and factored decoders are often clearer for ranges. The best implementation depends on the map and target, not on an Intel 8086-era rule.

2. Permission Logic

A logical permission may require several clauses, for example:

This is a product of single-literal conditions. Equivalently, shutdown = high_pressure OR high_temperature OR e_stop and RUN = NOT shutdown. These Boolean equations are useful for specification, but a safety-rated interlock also needs fault detection, defined de-energized behavior, diagnostics, validated hardware, and compliance with applicable safety standards. POS notation alone provides none of those guarantees.

The POS-to-NOR-NOR Connection

Just as SOP maps naturally to NAND-NAND logic, POS maps to NOR-NOR logic. The conversion uses De Morgan’s Laws and follows the same pattern.

Starting with our example:

Apply double negation:

Apply De Morgan’s to the outer bar (product becomes sum, each factor is complemented):

Each $\overline{(A + B + \overline{C})}$ is a NOR operation (after accounting for the complemented inputs), and the outer expression is also a NOR. The result is a two-level NOR-NOR circuit.

The structural pairing is the key insight: SOP can map to NAND-NAND, and POS can map to NOR-NOR by De Morgan’s laws. It does not force the implementation. A library may favor particular cells, and synthesis may factor or remap the expression.

SOP vs. POS: When to Use Which

For the example, canonical POS has three maxterms and canonical SOP has five minterms. After minimization, POS has two clauses. That makes POS attractive for this function, subject to target mapping and timing.

Conclusion

The Product of Sums teaches you to look at the zeros of a problem — the exceptions, the errors, the forbidden states. By mastering both POS and SOP, you gain the flexibility to choose the most efficient implementation for any function, whether that means fewer gates, lower propagation delay, or a better fit for your target technology.

Next in this series: simplify any function visually with Karnaugh maps, or open the OR Gate component reference and wire up the OR-AND circuit from this article.