D Latch with Clock Circuit Simulator

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您将学到什么

Distinguish transparent mode (clock high) from hold mode (clock low).
Trace D's effect on Q only while clock is high.
Recognize that latches are level-sensitive, not edge-triggered.
Understand setup/hold requirements around the clock falling edge.
Build flip-flops by chaining two latches with opposite clock phases.

工作原理

A clocked D latch adds a clock (or enable) input to the basic D latch. When clock = 1 (high), the latch is transparent — Q follows D directly. When clock = 0 (low), the latch is opaque — Q holds the last value it captured before the clock fell.

This level-sensitive behaviour is the defining feature of a latch (vs. a flip-flop, which is edge-triggered). The latch "opens" while the clock is high, letting D pass through; when the clock goes low, it "closes," trapping whatever D was at that moment.

Key timing considerations: - Transparency hazard: While clock is high, glitches on D propagate to Q. This is why latches are dangerous in synchronous design — output is sensitive to D for the full clock-high duration. - Setup/hold: D must be stable before and after the clock falls (the closing edge), or the latch may capture a wrong value or even enter a metastable state.

Latches were the standard storage element in early CPUs (Intel 4004, 8008) and are still used in master-slave flip-flops internally. Modern synchronous designs prefer edge-triggered flip-flops because their sample-on-edge behaviour is glitch-immune.

真值表

Latch behaviour by clock state. Q' is the previous Q value (memory).

输入		输出
CLK	D	Q
0	0	0	CLK low — Q holds previous value (here Q' = 0)
0	1	0	CLK low — Q holds. D's change ignored.
1	0	0	CLK high, D=0 → Q follows D = 0 (transparent)
1	1	1	CLK high, D=1 → Q follows D = 1 (transparent)

布尔表达式

Q_{next} = (\text{CLK} \cdot D) + (\overline{\text{CLK}} \cdot Q)

When CLK = 1, Q follows D; when CLK = 0, Q holds its previous value.

逐步尝试

在上方嵌入式电路中设置输入，然后阅读预期结果并验证。

1

CLK = 0 → 1 D = 1

预期: Q = 1

您将看到: Bring clock high while D = 1 — Q immediately follows. Transparent mode.
2

CLK = 1 D = 1 → 0

预期: Q = 0

您将看到: While clock is still high, change D — Q changes too. Latch is transparent throughout the high phase.
3

CLK = 1 → 0 D = 0

预期: Q = 0 (held)

您将看到: Clock falls to 0 — latch closes, Q holds whatever it was at the falling edge (here, 0). Now changes to D have no effect.
4

CLK = 0 D = 0 → 1

预期: Q = 0 (still held)

您将看到: Clock low, change D from 0 to 1 — Q stays 0. The latch ignores D in hold mode. Bring clock high again to capture the new D.

使用的组件

实际应用

Master-slave flip-flop construction. A D flip-flop is two D latches in series: master latches when clock is low, slave latches when clock is high. The combination samples on the clock edge.

Address latch enable (ALE). Some processors multiplex address and data on the same bus; an external D latch with ALE as the clock captures the address phase.

Wave-pipelined logic. High-speed designs sometimes use latch-based pipelines (instead of flip-flop pipelines) to overlap stage timing and squeeze more performance per clock cycle.

FIFO write enable. A FIFO's write-enable pulse can be used as a latch clock to capture the data into the head pointer.

Older microcontroller register files. Pre-1990s register files often used latches; modern ones use edge-triggered flip-flops.

常见问题

Why is the D latch transparent rather than edge-triggered?

It's the simpler design — pass-through when enabled, hold when disabled. Edge-triggering (sampling only on a transition) requires more sophisticated internal logic (typically two cascaded latches), but eliminates the transparency-hazard risk.

What happens if D changes while clock is high?

Q changes too. The latch is transparent during the high phase. This is why purely latch-based designs are tricky: the next stage sees Q glitching whenever D glitches. Synchronous designs prefer edge-triggered flip-flops for this reason.

What's setup time for a D latch?

The minimum stable time D must precede the clock's falling edge (the 'closing' edge) so the latch correctly captures D. Below this time, the latch may enter metastability or capture an indeterminate value.

How is this different from a D flip-flop?

A latch is transparent during the entire high phase of clock; a flip-flop samples only on the rising (or falling) edge of clock and ignores D for the rest of the cycle. Flip-flops are glitch-immune; latches are not.

Where would I prefer latches over flip-flops?

In wave-pipelined or asynchronous designs, latches can squeeze more timing per cycle. Some standard cell libraries also offer fast L1/L2 latches for low-power applications. For 99% of synchronous designs, flip-flops are the right choice.