8-to-3 Priority Encoder
Eight-input priority encoder with 3-bit output. Advanced data compression and interrupt handling concepts.
您将学到什么
- Encode the highest-priority of 8 inputs into a 3-bit code.
- Read the 8-to-3 priority truth table — focusing on the priority masking.
- Use the V output to distinguish 'I0 active' from 'no input active'.
- Recognise 8-to-3 priority encoders inside the Intel 8259 PIC and equivalent.
- Apply for interrupt control, leading-1 detection, and resource allocation.
工作原理
An 8-to-3 priority encoder takes 8 inputs (I0–I7, with I7 highest priority) and outputs a 3-bit code (Y2 Y1 Y0) indicating the index of the highest-priority active input. A separate valid (V) output signals whether any input was active.
If I7 is high, output is 111 regardless of other inputs. Else if I6 is high, output is 110. Else if I5 is high, output is 101. ... and so on down to I0 (output 000). If no input is high, V = 0.
Boolean expressions show the priority masking pattern: each output bit is OR'd over the inputs whose binary index has that bit set, but masked by inverted higher-priority inputs.
8-to-3 priority encoders are workhorses of CPU interrupt controllers. The classic Intel 8259 PIC implements this exact function plus cascading and acknowledgement.
真值表
Showing rows where each input is the highest active. Higher-priority inputs mask lower ones.
| 输入 | 输出 | ||||
|---|---|---|---|---|---|
| Active Highest | Y2 | Y1 | Y0 | V | |
| 0 | 0 | 0 | 0 | 0 | No inputs — V=0 |
| 0 | 0 | 0 | 0 | 1 | Only I0 → 000, V=1 |
| 1 | 0 | 0 | 1 | 1 | I1 highest → 001 |
| 1 | 0 | 1 | 0 | 1 | I2 highest → 010 |
| 1 | 0 | 1 | 1 | 1 | I3 highest → 011 |
| 1 | 1 | 0 | 0 | 1 | I4 highest → 100 |
| 1 | 1 | 0 | 1 | 1 | I5 highest → 101 |
| 1 | 1 | 1 | 0 | 1 | I6 highest → 110 |
| 1 | 1 | 1 | 1 | 1 | I7 highest → 111 |
布尔表达式
High bit: set if any of the upper four inputs is active.
Middle bit: set when an upper input is active, with priority masking from higher bits.
Valid: OR of all inputs. Tells the consumer whether the encoded output is meaningful.
逐步尝试
在上方嵌入式电路中设置输入，然后阅读预期结果并验证。
- 1I0 = 1预期:
Y2Y1Y0=000, V=1您将看到: Lowest priority — output 0, valid bit confirms it's a real signal not 'no input.' - 2I0 = 1 I3 = 1预期:
Y2Y1Y0=011, V=1您将看到: Both I0 and I3 high. I3 has higher priority → output 011 (= 3). I0 is masked. - 3I7 = 1 I0 = 1预期:
Y2Y1Y0=111, V=1您将看到: I7 has the highest priority of all 8 inputs. Even with I0 active, the output is 111 (= 7). - 4预期:
Y2Y1Y0=000, V=0您将看到: No inputs active — V drops to 0 to signal 'no real event.' Without V the consumer would mistake this for 'I0 active.'
使用的组件
实际应用
8-line interrupt controller. The 8259 PIC takes 8 IRQ lines, encodes the highest-priority active one, and presents it as the active vector for the CPU to fetch.
Floating-point leading-1 detection. After arithmetic, the leading-1 detection of an 8-bit field uses an 8-to-3 priority encoder (often extended to 24 or 53 bits for IEEE 754).
8-source bus arbitration. A bus controller with 8 requesters uses an 8-to-3 priority encoder to grant the bus to the highest-priority requester.
Priority-based resource allocation. Allocating from 8 resource slots: a free-list bitmap fed to a priority encoder yields the lowest-numbered free slot in O(1).
Cache replacement policy. LRU bits across 8 cache ways feed a priority encoder to identify the least-recently-used way for eviction.