D Flip-Flop with Controls (Set/Reset/Enable) Simulator

您将学到什么

工作原理

真值表

布尔表达式

逐步尝试

使用的组件

实际应用

常见问题

交互式模拟器需要 JavaScript

启用 JavaScript 即可加载实时电路。下方真值表描述了该电路的行为。

Use asynchronous Set and Reset to override clock-driven behaviour.
Use synchronous Enable to gate clock edges.
Recognise the priority order: Reset > Set > Enable > Clock.
Apply asynchronous reset for power-on initialization.
Apply Enable for register write-enable in a register file.

A D flip-flop with controls adds three common features to the basic edge-triggered DFF:

- Set (asynchronous): When asserted, forces Q = 1 immediately, regardless of clock. Used for power-on initialization or explicit overrides. - Reset (asynchronous): When asserted, forces Q = 0 immediately, regardless of clock. Used for system reset propagation. - Enable (synchronous): When low, the flip-flop ignores the clock edge and holds its current value; when high, it operates normally and captures D on the edge.

Priority typically: Reset > Set > Enable > Clock. So a high reset wins over set or normal operation.

This cell is the standard library element for register design. Almost every register in a real CPU uses DFFs with at least Reset (for power-on initialization) and Enable (for write-control logic). Set is less common but useful for default-1 power-on values.

The Enable input is particularly important: it's how a register's write-enable signal gates the flip-flop. Without Enable, you'd need an extra MUX feeding back Q to itself when not writing — wasteful in area and timing.

Behaviour by control-input state. Async controls override clock; Enable gates clock.

Q_{n+1} = \begin{cases} 0 & \text{if RST} \\ 1 & \text{if SET} \\ D & \text{if EN \& \uparrow CLK} \\ Q_n & \text{otherwise} \end{cases}

Priority cascade: async controls win over clock-driven behaviour.

在上方嵌入式电路中设置输入，然后阅读预期结果并验证。

1

RST = 1 SET = 0 EN = 1 CLK = any

预期: Q = 0

您将看到: Reset asserted — Q goes immediately to 0, regardless of clock or D. Async means right now, not waiting for an edge.
2

RST = 0 SET = 1 EN = 0 CLK = stopped

预期: Q = 1

您将看到: Set asserted with clock stopped — Q goes to 1 anyway. Async controls don't need a clock.
3

RST = 0 SET = 0 EN = 0 CLK = running D = varying

预期: Q frozen at last value

您将看到: Enable low — flip-flop ignores all clock edges. D's changes have no effect. Useful for stalled pipeline stages.
4

RST = 0 SET = 0 EN = 1 CLK = rising edge D = 1

预期: Q = 1

您将看到: Normal write — Enable high, clock rises with D=1, Q captures 1. The standard register-write pattern.

D Flip-Flop with Controls

×1

Output Light

×2

CPU register file. Every register has a write-enable that gates whether each clock cycle captures new data. Implemented via the Enable input on each DFF.

System reset distribution. A global async reset signal connects to every flip-flop's Reset input, ensuring all state initializes simultaneously at power-on or external reset.

Configuration-bit storage with default values. Some configuration bits should default to 1 (e.g., interrupt-enable in some architectures); they use Set to initialize at reset.

Pipeline stall flip-flops. When a pipeline stage stalls, downstream flip-flops keep their values via Enable=0; new data isn't captured until the stall clears.

State-machine reset states. FSMs reset to a known initial state via async Reset on the state-encoding flip-flops.

Reset asserted → Q = 0 immediately, async

Set asserted → Q = 1 immediately, async

Enable low → clock edge ignored, Q holds

Enable high, rising clock, D=1 → Q = 1 (captured)

Enable high, rising clock, D=0 → Q = 0

Why are Set and Reset asynchronous instead of synchronous?

Async lets them work even when the clock is stopped — critical for power-on reset (the clock might not be stable yet) and for emergency resets that must take effect immediately. Synchronous reset is also possible but requires a running clock.

What's the priority if both Set and Reset are asserted?

Convention varies, but typically Reset wins. The flip-flop ends up at 0. Some libraries make this configurable; some forbid the combination as undefined behaviour.

How does Enable differ from gating the clock?

Gating the clock (clock-and-something) creates clock-domain issues — different parts of the chip see different clocks, which complicates timing analysis. Enable cleanly multiplexes between holding and capturing without disrupting the clock signal. Modern designs prefer Enable over clock gating for this reason.

Can I implement Enable from a basic DFF + MUX?

Yes — a 2-to-1 MUX feeding D, with one input being Q (held) and the other being the new data, controlled by Enable. Functionally equivalent. Standard cell libraries provide DFF-with-enable as a single optimized cell.

What's the typical setup-time difference with controls vs. without?

Negligible. The Set/Reset paths add small async logic at the output stage; Enable adds a MUX in front of D. Both are well-characterized in standard cell libraries — synthesis tools account for them automatically.