8-to-1 Multiplexer Circuit Simulator

交互式模拟器需要 JavaScript

启用 JavaScript 即可加载实时电路。下方真值表描述了该电路的行为。

您将学到什么

Address 8 data inputs using a 3-bit select code.
Read the 8-to-1 MUX behavioural table — output follows the selected input.
Build an 8-to-1 MUX as a tree of 2-to-1 MUXes.
Use an 8-to-1 MUX as a 3-input LUT to realise any Boolean function of 3 variables.
Identify where wide MUXes appear: register files, audio switches, BIST.

工作原理

An 8-to-1 multiplexer routes one of eight data inputs (D0–D7) to a single output, based on a 3-bit select code (S2 S1 S0). Three select bits address 2³ = 8 inputs.

The select-to-data mapping is the binary value of S2S1S0: - 000 → D0, 001 → D1, 010 → D2, 011 → D3 - 100 → D4, 101 → D5, 110 → D6, 111 → D7

Boolean expression: Y is a sum of 8 minterms, each AND'ing one data input with the matching 3-bit select decode. SOP form: Y = ¬S2¬S1¬S0·D0 + ¬S2¬S1S0·D1 + ... + S2S1S0·D7.

An 8-to-1 MUX can be built as a tree of seven 2-to-1 MUXes (or two 4-to-1s feeding a 2-to-1 final stage). Either decomposition gives the same function.

The lookup-table view: the 8 data inputs hold the 8 output values of any 3-variable Boolean function; the 3 select bits are the function's input variables. This makes any 3-input combinational function expressible as an 8-to-1 MUX with appropriate hardcoded data inputs.

真值表

Select code S2S1S0 chooses which of D0..D7 reaches Y. Showing each select case (data inputs all set to 1 to make selection visible).

输入			输出
S2	S1	S0	Y (when D_select=1)
0	0	0	1	Select 0 → Y = D0
0	0	1	1	Select 1 → Y = D1
0	1	0	1	Select 2 → Y = D2
0	1	1	1	Select 3 → Y = D3
1	0	0	1	Select 4 → Y = D4
1	0	1	1	Select 5 → Y = D5
1	1	0	1	Select 6 → Y = D6
1	1	1	1	Select 7 → Y = D7

布尔表达式

Y = \sum_{i=0}^{7} m_i(S_2,S_1,S_0) \cdot D_i

Where m_i is the i-th 3-variable minterm. Each term ANDs one D input with the unique select-code that addresses it.

逐步尝试

在上方嵌入式电路中设置输入，然后阅读预期结果并验证。

1

S2 = 0 S1 = 0 S0 = 0 D0 = 1

预期: Y = 1

您将看到: Select 000 routes D0. The other Ds are ignored.
2

S2 = 0 S1 = 1 S0 = 1 D3 = 1

预期: Y = 1

您将看到: Select 011 = 3 → routes D3. Watch the binary count of select correspond to data input index.
3

S2 = 1 S1 = 1 S0 = 1 D7 = 1

预期: Y = 1

您将看到: Select 111 = 7 → routes D7. The MUX has covered all 8 data inputs across the 8 select codes.
4

S2 = 0 S1 = 0 S0 = 1 D1 = 0

预期: Y = 0

您将看到: Select=001 routes D1=0. Output is the value of the addressed input — a high select doesn't itself drive Y high.

使用的组件

实际应用

Register file with 8 registers. Reading any of 8 registers uses an 8-to-1 MUX driven by a 3-bit register-address bus.

Audio source switching. A stereo amplifier switching between 8 input sources (CD, AUX1, AUX2, etc.) uses an 8-to-1 analog MUX with the source selector encoded as 3 bits.

Test multiplexer (BIST). Built-In Self-Test circuits use an 8-to-1 MUX to scan internal signals out for debug or test, with a 3-bit selector picking which signal to observe.

3-input Boolean function generator. Using an 8-to-1 MUX as a LUT lets you implement any 3-input function (256 possible) by hardcoding D0–D7.

Memory address decoders. Cycle through 8 memory pages or bank addresses with a 3-bit selector and an 8-to-1 MUX selecting which page's data is current.

常见问题

Why does an 8-to-1 MUX need 3 select bits?

log₂(8) = 3. Three bits encode 8 distinct select codes — one per data input. In general N-to-1 MUXes need ⌈log₂N⌉ select bits.

Can I build a 16-to-1 MUX from two 8-to-1s?

Yes. Two 8-to-1 MUXes (one for inputs 0–7, one for inputs 8–15), each using the lower 3 select bits, feed a 2-to-1 MUX selected by the highest bit. Total: 2 × 8-to-1 + 1 × 2-to-1.

How does this compare to ROM lookup?

An 8-to-1 MUX with hardcoded data inputs IS a tiny ROM. A 3-input ROM has 8 addressable locations — the MUX with frozen Ds is logically the same. Real ROMs scale to thousands of words; an 8-to-1 MUX scales only to 8.

What's the depth (number of gate delays) through an 8-to-1?

If built as a balanced tree of 2-to-1s: log₂(8) = 3 levels. If implemented as a single SOP layer of 8 minterms: 2 levels (AND then OR). Tree implementations have lower transistor count but more depth.

Is the data input width affected by the MUX size?

Standard MUXes route 1-bit signals. To MUX wider buses (e.g., 8 inputs of 16 bits each), use 16 parallel 8-to-1 MUXes — one per bit. The select lines are shared across all of them.