D Latch with Clock
D latch demonstration with clock enable and oscilloscope. Learn level-triggered memory storage and timing analysis.
Lo que aprenderás
- Distinguish transparent mode (clock high) from hold mode (clock low).
- Trace D's effect on Q only while clock is high.
- Recognize that latches are level-sensitive, not edge-triggered.
- Understand setup/hold requirements around the clock falling edge.
- Build flip-flops by chaining two latches with opposite clock phases.
Cómo funciona
A clocked D latch adds a clock (or enable) input to the basic D latch. When clock = 1 (high), the latch is transparent — Q follows D directly. When clock = 0 (low), the latch is opaque — Q holds the last value it captured before the clock fell.
This level-sensitive behaviour is the defining feature of a latch (vs. a flip-flop, which is edge-triggered). The latch "opens" while the clock is high, letting D pass through; when the clock goes low, it "closes," trapping whatever D was at that moment.
Key timing considerations: - Transparency hazard: While clock is high, glitches on D propagate to Q. This is why latches are dangerous in synchronous design — output is sensitive to D for the full clock-high duration. - Setup/hold: D must be stable before and after the clock falls (the closing edge), or the latch may capture a wrong value or even enter a metastable state.
Latches were the standard storage element in early CPUs (Intel 4004, 8008) and are still used in master-slave flip-flops internally. Modern synchronous designs prefer edge-triggered flip-flops because their sample-on-edge behaviour is glitch-immune.
Tabla de verdad
Latch behaviour by clock state. Q' is the previous Q value (memory).
| Entradas | Salida | ||
|---|---|---|---|
| CLK | D | Q | |
| 0 | 0 | 0 | CLK low — Q holds previous value (here Q' = 0) |
| 0 | 1 | 0 | CLK low — Q holds. D's change ignored. |
| 1 | 0 | 0 | CLK high, D=0 → Q follows D = 0 (transparent) |
| 1 | 1 | 1 | CLK high, D=1 → Q follows D = 1 (transparent) |
Expresión booleana
When CLK = 1, Q follows D; when CLK = 0, Q holds its previous value.
Pruébalo paso a paso
Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.
- 1CLK = 0 → 1 D = 1Esperado:
Q = 1Lo que verás: Bring clock high while D = 1 — Q immediately follows. Transparent mode. - 2CLK = 1 D = 1 → 0Esperado:
Q = 0Lo que verás: While clock is still high, change D — Q changes too. Latch is transparent throughout the high phase. - 3CLK = 1 → 0 D = 0Esperado:
Q = 0 (held)Lo que verás: Clock falls to 0 — latch closes, Q holds whatever it was at the falling edge (here, 0). Now changes to D have no effect. - 4CLK = 0 D = 0 → 1Esperado:
Q = 0 (still held)Lo que verás: Clock low, change D from 0 to 1 — Q stays 0. The latch ignores D in hold mode. Bring clock high again to capture the new D.
Componentes utilizados
Aplicaciones en el mundo real
Master-slave flip-flop construction. A D flip-flop is two D latches in series: master latches when clock is low, slave latches when clock is high. The combination samples on the clock edge.
Address latch enable (ALE). Some processors multiplex address and data on the same bus; an external D latch with ALE as the clock captures the address phase.
Wave-pipelined logic. High-speed designs sometimes use latch-based pipelines (instead of flip-flop pipelines) to overlap stage timing and squeeze more performance per clock cycle.
FIFO write enable. A FIFO's write-enable pulse can be used as a latch clock to capture the data into the head pointer.
Older microcontroller register files. Pre-1990s register files often used latches; modern ones use edge-triggered flip-flops.