Basic RAM Memory System Circuit Simulator

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启用 JavaScript 即可加载实时电路。下方真值表描述了该电路的行为。

您将学到什么

Recognize a RAM as addressable storage with read and write ports.
Use address inputs to select a memory word.
Use write-enable to strobe data into the addressed word.
Read back stored data from any address.
Connect this to CPU caches, microcontroller scratchpads, and FPGA BRAMs.

工作原理

A basic RAM memory system stores data at addressable locations. The fundamental operations are write (store data at an address) and read (retrieve data from an address). This circuit demonstrates the simplest functional RAM — typically 4 to 16 words, each a few bits wide, with explicit address, data-in, write-enable, and data-out lines.

Write cycle: 1. Address inputs select a word location. 2. Data inputs present the value to store. 3. Write-enable strobes; on the active edge, the addressed word's flip-flops capture the data.

Read cycle: 1. Address inputs select a word. 2. The output MUX routes the addressed word's flip-flops to the data-out lines.

Real RAM uses much denser storage cells (DRAM uses one transistor + capacitor per bit; SRAM uses 6 transistors per bit). The conceptual structure — addressable storage, decoder for address-to-word selection, output MUX — is the same as this simplified model.

Key insight: a RAM is essentially a register file with address-decoded write-enable and address-controlled output MUX. Each "word" is a small register; the decoder picks which one to write; the MUX picks which one to read.

逐步尝试

在上方嵌入式电路中设置输入，然后阅读预期结果并验证。

1

Address = 00 Data In = 1010 Write-Enable = 1 Clock = rising

预期: RAM[0] = 1010

您将看到: Write 1010 to address 0. Read it back by setting address=00 and removing write-enable.
2

Address = 01 Data In = 0101 Write-Enable = 1 Clock = rising

预期: RAM[1] = 0101

您将看到: Write 0101 to address 1. Each address holds independent data.
3

Address = 00 Write-Enable = 0

预期: Data Out = 1010

您将看到: Read address 0 — data port reflects the previously stored 1010. Read is asynchronous (no clock needed) in this simple model.
4

Address = 10 Data In = 1111 Write-Enable = 0

预期: RAM[2] unchanged

您将看到: Write-enable low — even though Data In is presented, RAM doesn't capture. Reads of address 2 return whatever was previously written there (or 0 at power-on).

使用的组件

实际应用

CPU L1 / L2 / L3 caches. Caches are SRAMs with set-associative organization. The base storage is the same address-decoded register array.

Microcontroller scratchpad RAM. On-chip SRAM for variables and stack — typically 1 KB to 1 MB, accessed in single cycles.

FPGA block RAMs. Dedicated RAM blocks in FPGAs (e.g., Xilinx BRAM, Intel M9K) are SRAM cells with the same address/data/we structure exposed to user logic.

Frame buffers in graphics chips. Display frame buffers are RAMs with x/y coordinates as the address; pixel data flows through the data port.

Lookup tables (LUTs) in instruments. Function generators store waveform samples in RAM; address increments through samples to produce the analog output.

常见问题

How does the address actually select a word?

An address decoder (like the 2-to-4 or 3-to-8 decoders in earlier templates) converts the binary address into one-hot select signals. Each select line gates the write-enable to one specific word's flip-flops. Output MUXes use the same address to route the selected word's flip-flops to the data-out lines.

What's the difference between RAM and ROM?

RAM is read/write — you can change the contents at runtime. ROM is read-only — the contents are fixed at manufacturing or programming time. Internally, ROM uses simpler storage (transistors hardwired to 0 or 1) since no write circuitry is needed.

Why is RAM data lost on power-off?

Standard SRAM and DRAM are volatile — the storage cells (cross-coupled transistors or capacitor charge) need power to maintain their state. Non-volatile memory (Flash, EEPROM, FRAM) uses different physics that retain data without power.

How do real RAMs scale to gigabytes?

Hierarchical addressing. A 16 GB DRAM has multiple banks, each with multiple rows and columns. The address decodes into bank/row/column selects, and the row's data is fetched into a row buffer for column access. The single-cycle simplified model breaks down at scale; real RAMs have multi-cycle access patterns.

What's read-write timing?

In real RAMs, reads have a delay (access time) before data is valid; writes have a setup/hold around the clock edge. Multi-port RAMs allow simultaneous read and write to different addresses. CPUs typically have 1–4 cycle access for L1 cache.