Buffer and Tri-State Demo
Buffer circuits demonstrating signal amplification and tri-state control. Learn about high-impedance states and bus systems.
您将学到什么
- Distinguish a plain buffer (drive amplification, no logic change) from a tri-state buffer (high-impedance output state).
- Recognise the three states of a tri-state buffer's output: 0, 1, and Z (high impedance).
- Explain why tri-state outputs enable shared buses with multiple drivers.
- Read the tri-state truth table including the Z row when enable = 0.
- Identify buffers in real systems: clock trees, memory buses, register files.
工作原理
Two related but distinct components in one demo: the plain buffer (Y = A — same logic value, just with stronger drive) and the tri-state buffer (Y = A when enable is 1, but Y is high-impedance — "floating" — when enable is 0).
A plain buffer doesn't change the logic level; it just amplifies. Why bother? Because gate outputs have limited drive strength. A signal feeding many inputs, or a long wire with high capacitance, slows down without enough drive. A buffer chain restores edge speed.
The tri-state buffer adds a third output state on top of 0 and 1: Z (high impedance), where the output is electrically disconnected. This is what enables bus sharing — multiple devices wired to the same bus, with only one driving at a time. Each device has its own tri-state output enabled by chip-select; the inactive devices float their pins, leaving the bus to whichever one is enabled.
Without tri-state, you'd need separate wires from every source to every destination — a wiring nightmare. Tri-state buffers reduce that to a shared bus with arbitration logic.
真值表
The tri-state buffer adds an enable input. When EN = 0 the output disconnects (Z); when EN = 1 it passes the input through.
| 输入 | 输出 | ||
|---|---|---|---|
| A | EN | Y | |
| 0 | 0 | 0 | EN low — Y is high-Z (shown as 0 in this simulator) |
| 1 | 0 | 0 | EN low — Y is high-Z regardless of A |
| 0 | 1 | 0 | EN high — Y follows A |
| 1 | 1 | 1 | EN high — Y follows A |
布尔表达式
Plain buffer: output equals input. Drive strength differs but logic is unchanged.
Tri-state buffer: output follows A only when enabled, otherwise high-impedance.
Conditional pass-through. Standard truth tables can't express Z; the buffer is a special component, not a Boolean function.
逐步尝试
在上方嵌入式电路中设置输入，然后阅读预期结果并验证。
- 1A_buffer = 0预期:
Y = 0您将看到: Plain buffer pass-through: output follows input directly. No inversion, just drive strength. - 2A_buffer = 1预期:
Y = 1您将看到: Buffer output goes high. Logically identical to a wire — just with more current available. - 3A_tri = 1 EN = 0预期:
Y = Z (high-Z)您将看到: Enable low — tri-state output disconnects. In a real circuit this lets another driver take over the wire. The simulator may display as 0 or as a special floating state. - 4A_tri = 1 EN = 1预期:
Y = 1您将看到: Enable high — tri-state acts like a regular buffer, passing A through.
使用的组件
实际应用
Memory data buses. RAM and ROM chips share a common data bus. Each chip's data pins are tri-state and only enabled when its chip-select is asserted. The CPU reads from whichever chip is currently selected.
CPU register file output. Internal CPU registers all connect to a shared internal bus through tri-state buffers. The instruction decoder enables the register being read, suppressing the others to high-Z.
Multi-master bus arbitration. PCIe, AXI, AHB and similar protocols use tri-state (or muxed equivalents) so multiple bus masters can take turns driving the bus.
Driver chains for clock distribution. A clock signal driving thousands of flip-flops needs successive buffer stages — a single inverter can't drive that load fast enough. Tree-structured buffer fan-out is standard practice.
ATE (test-equipment) probes. Test pins use tri-state to selectively connect to the device under test without loading other lines.