4-Bit Asynchronous Ripple Counter (T-Type Flip-Flops)
Counts from 0000 to 1111 (0-15) using cascaded T-type flip-flops. Each flip-flop triggers the next, creating a "ripple" effect. Binary output: Bit3 Bit2 Bit1 Bit0 (MSB to LSB)
您将学到什么
- Chain T flip-flops to count clock pulses in binary.
- Recognise that each T-FF divides its clock-input frequency by 2.
- Trace the binary counting sequence: 0000 → 0001 → ... → 1111 → 0000.
- Identify ripple delay: higher bits update later than lower bits within a count step.
- Compare asynchronous (ripple) vs. synchronous counters and pick the right one.
工作原理
An asynchronous ripple counter counts clock pulses by chaining toggle (T) flip-flops, where each flip-flop's output becomes the clock for the next. The result: bit 0 toggles on every clock edge, bit 1 toggles on every other (when bit 0 falls), bit 2 every fourth, bit 3 every eighth — exactly the binary counting pattern.
With four T-FFs, the counter cycles through 0000 → 0001 → 0010 → ... → 1111 → 0000 (decimal 0 through 15, then wraps). One full cycle of bit 3 takes 16 clock pulses.
Why "ripple"? Because the changes don't happen simultaneously — they ripple from bit 0 outward. Each flip-flop has a small propagation delay; bit 1 doesn't toggle until bit 0's output settles, and so on. For wide counters this means the highest bits update significantly later than the lowest, which can cause glitches during the brief transition.
The trade-off is simplicity. A ripple counter needs only N T-FFs and zero extra combinational logic. A synchronous counter, by contrast, has all flip-flops clocked together but needs an AND tree to compute each bit's toggle-enable based on lower bits. Synchronous is faster and glitch-free; asynchronous is smaller and easier to wire.
Note: Although this template's category is listed as "Combining and Derived Gates" in the database, this is fundamentally a sequential circuit — its state depends on history, not just current inputs. There's no static truth table; behaviour is described over time.
逐步尝试
在上方嵌入式电路中设置输入，然后阅读预期结果并验证。
- 1Clock = running预期:
Bit 0 toggles every clock edge您将看到: Watch only bit 0: it flips with every active edge. This is the basic T-FF behaviour — the counter's least-significant bit. - 2Clock = after 2 edges预期:
Bit 1 = 1, Bit 0 = 0 (= binary 0010 = 2)您将看到: When bit 0 falls from 1 to 0, bit 1's clock sees an edge and toggles. Two clock pulses → count is 2. - 3Clock = after 8 edges预期:
Bit 3 = 1, others = 0 (= binary 1000 = 8)您将看到: Bit 3 first lights up on the 8th clock pulse. The cascade has propagated all the way to the most-significant bit. - 4Clock = after 16 edges预期:
All bits = 0 (= 0000)您将看到: The counter wraps from 1111 back to 0000 — one full cycle of bit 3 corresponds to 16 clock pulses. The next pulse starts the cycle again.
使用的组件
实际应用
Frequency division. Each T-FF divides its input frequency by 2. A 4-bit ripple counter divides the clock by 16 — useful for generating slower clocks from a fast master oscillator.
Simple digital clocks. A divider chain converts a crystal oscillator (e.g., 32.768 kHz) down to 1 Hz for second ticks, then through more dividers to minutes/hours. Watch ICs use exactly this pattern.
LED scanning matrices. A small ripple counter cycles through row addresses for multiplexed LED displays, refreshing one row per clock.
Address generation in test patterns. ATE (automatic test equipment) uses ripple counters to walk through memory addresses during march tests for stuck-at faults.
Pulse counting / event counting. Counting external events (button presses, photon counts, etc.) where output speed isn't critical and circuit simplicity matters.