8-to-3 Priority Encoder Circuit Simulator

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Lo que aprenderás

Encode the highest-priority of 8 inputs into a 3-bit code.
Read the 8-to-3 priority truth table — focusing on the priority masking.
Use the V output to distinguish 'I0 active' from 'no input active'.
Recognise 8-to-3 priority encoders inside the Intel 8259 PIC and equivalent.
Apply for interrupt control, leading-1 detection, and resource allocation.

Cómo funciona

An 8-to-3 priority encoder takes 8 inputs (I0–I7, with I7 highest priority) and outputs a 3-bit code (Y2 Y1 Y0) indicating the index of the highest-priority active input. A separate valid (V) output signals whether any input was active.

If I7 is high, output is 111 regardless of other inputs. Else if I6 is high, output is 110. Else if I5 is high, output is 101. ... and so on down to I0 (output 000). If no input is high, V = 0.

Boolean expressions show the priority masking pattern: each output bit is OR'd over the inputs whose binary index has that bit set, but masked by inverted higher-priority inputs.

8-to-3 priority encoders are workhorses of CPU interrupt controllers. The classic Intel 8259 PIC implements this exact function plus cascading and acknowledgement.

Tabla de verdad

Showing rows where each input is the highest active. Higher-priority inputs mask lower ones.

Entradas	Salida
Active Highest	Y2	Y1	Y0	V
0	0	0	0	0	No inputs — V=0
0	0	0	0	1	Only I0 → 000, V=1
1	0	0	1	1	I1 highest → 001
1	0	1	0	1	I2 highest → 010
1	0	1	1	1	I3 highest → 011
1	1	0	0	1	I4 highest → 100
1	1	0	1	1	I5 highest → 101
1	1	1	0	1	I6 highest → 110
1	1	1	1	1	I7 highest → 111

Expresión booleana

Y_2 = I_7 + I_6 + I_5 + I_4

High bit: set if any of the upper four inputs is active.

Y_1 = I_7 + I_6 + \overline{I_5}\overline{I_4}(I_3 + I_2)

Middle bit: set when an upper input is active, with priority masking from higher bits.

V = I_7 + I_6 + I_5 + I_4 + I_3 + I_2 + I_1 + I_0

Valid: OR of all inputs. Tells the consumer whether the encoded output is meaningful.

Pruébalo paso a paso

Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.

1

I0 = 1

Esperado: Y2Y1Y0=000, V=1

Lo que verás: Lowest priority — output 0, valid bit confirms it's a real signal not 'no input.'
2

I0 = 1 I3 = 1

Esperado: Y2Y1Y0=011, V=1

Lo que verás: Both I0 and I3 high. I3 has higher priority → output 011 (= 3). I0 is masked.
3

I7 = 1 I0 = 1

Esperado: Y2Y1Y0=111, V=1

Lo que verás: I7 has the highest priority of all 8 inputs. Even with I0 active, the output is 111 (= 7).
4

Esperado: Y2Y1Y0=000, V=0

Lo que verás: No inputs active — V drops to 0 to signal 'no real event.' Without V the consumer would mistake this for 'I0 active.'

Componentes utilizados

Input Switch

×8

Priority Encoder (8-to-3)

×1

Output Light

×4

Aplicaciones en el mundo real

8-line interrupt controller. The 8259 PIC takes 8 IRQ lines, encodes the highest-priority active one, and presents it as the active vector for the CPU to fetch.

Floating-point leading-1 detection. After arithmetic, the leading-1 detection of an 8-bit field uses an 8-to-3 priority encoder (often extended to 24 or 53 bits for IEEE 754).

8-source bus arbitration. A bus controller with 8 requesters uses an 8-to-3 priority encoder to grant the bus to the highest-priority requester.

Priority-based resource allocation. Allocating from 8 resource slots: a free-list bitmap fed to a priority encoder yields the lowest-numbered free slot in O(1).

Cache replacement policy. LRU bits across 8 cache ways feed a priority encoder to identify the least-recently-used way for eviction.

Preguntas frecuentes

Why is priority masking needed?

Because multiple inputs may go high simultaneously. Without masking, the encoder would output garbage. Priority masking ensures deterministic behaviour: pick the highest-numbered (or lowest-numbered, depending on design) active input.

How is this used in the Intel 8259 PIC?

The 8259 has 8 IRQ inputs, an 8-to-3 priority encoder, plus mask registers and acknowledgement logic. When IRQs fire, the priority encoder picks the highest unmasked one and presents its vector to the CPU. Modern x86 CPUs replaced the 8259 with the APIC, but the priority-encoder principle is the same.

Why are larger priority encoders harder to build?

Wider priority encoders have longer carry-like masking chains. A 32-to-5 priority encoder uses ~64 gates and has higher delay. Modern designs split into pre-encoded subgroups: 4-bit groups use 4-to-2 encoders, then a select picks the active group.

What if I want lowest-priority instead?

Build a similar circuit but with the priority direction reversed: I0 has highest priority, I7 has lowest. Boolean expressions are mirrored. Some encoder ICs have a configuration pin that selects high-MSB-first vs high-LSB-first.

Can I cascade two 8-to-3 encoders to get 16-to-4?

Yes. The two encoders run in parallel; their valid outputs feed a chooser that picks the higher-priority encoder's output. The 4-bit result is the chosen encoder's index (1 bit) concatenated with its 3-bit output. Common in older PICs and resource allocators.