3-Bit Binary Adder (Gate-Level) Circuit Simulator

学べること

仕組み

真理値表

ブール式

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実世界での応用

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Build a 3-bit adder from XOR, AND, OR gates without using full-adder primitives.
Trace the gate-level critical path through 3 ripple stages.
Compare gate-level and component-level views of the same circuit.
Understand how carry-out is produced from a half-adder + OR pattern.
Apply gate-level analysis to optimize for transistor count or speed.

This 3-bit adder is built from individual gates (XOR, AND, OR) rather than packaged full-adder components. The internal structure is the same as the full-adder version, just with the per-stage logic exposed.

Each bit position uses the standard half-adder (XOR + AND) on the operand bits, plus an OR-of-carries pattern for the carry-out: - Sum bit: Si = (Ai ⊕ Bi) ⊕ Cini - Carry-out: Couti = (Ai · Bi) + ((Ai ⊕ Bi) · Cini)

Decomposing into gates makes the timing path visible: each full-adder's worst case is XOR (1) + AND (1) + OR (1) = ~3 gate delays. Across 3 bits that's ~9 gate delays worst case.

The educational benefit is seeing why the circuit produces correct binary addition — every gate's contribution to sum and carry is laid out. The cost is more wiring complexity than the component-based version.

Same I/O as the component-based 3-bit adder. Selected key rows.

S_i = A_i \oplus B_i \oplus C_{in,i}

Sum at bit i — XOR of all three.

C_{out,i} = A_i B_i + C_{in,i}(A_i \oplus B_i)

Carry-out at bit i — AND of operand bits OR carry-in ANDed with the operand XOR.

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

A = 111 B = 001

期待値: S = 1000

観察ポイント: 7 + 1 = 8. Carry chain: bit 0 generates, bit 1 propagates, bit 2 propagates → S3 = 1.
2

A = 010 B = 010

期待値: S = 0100

観察ポイント: 2 + 2 = 4. Bit 1 generates a carry that goes into bit 2, making S2 = 1.
3

A = 111 B = 111

期待値: S = 1110

観察ポイント: Max sum. Each stage's carry adds another '1' at the top.
4

A = 101 B = 010

期待値: S = 0111

観察ポイント: 5 + 2 = 7. No carry out of any stage; the inputs don't both have 1 at the same column.

Custom CPU adder cells. When designing your own ALU at the transistor level, you start from gate-level full-adder layouts to optimize for area, speed, or power.

FPGA carry chain logic. FPGAs pack gate-level full-adder cells into specialized carry-chain hardware that's faster than building from look-up tables.

Educational comparator with the component version. Side-by-side, the gate-level vs. component-level versions show abstraction layers — same function, different representation.

Timing analysis exercises. Identifying the critical path through the gate-level circuit teaches static timing analysis fundamentals.

7 + 7 = 14 (max)

Why build at gate level when full-adder components exist?

Educational clarity, transistor-level optimisation, or non-standard cell libraries. Gate-level views show the actual logic; component views hide it. Both approaches produce identical circuits in the end.

How many transistors total in CMOS?

Each full-adder is ~28 transistors. Three stages ≈ 84 transistors. The component version uses the same internally — packaging doesn't change the underlying hardware.

What's the critical path?

Cin0 → bit 0 carry-out → bit 1 carry-out → bit 2 carry-out → S3. About 6 gate delays end-to-end (each carry stage is 2 levels of logic).

Can I share gates between stages?

Some optimizations exist (e.g., Manchester carry-chain shares pass transistors), but at the basic SOP level, each stage is independent. Custom layouts can squeeze out a few transistors via shared structures.

Why does the simulator show duplicate gates per stage?

Each stage needs its own XOR (for sum), AND (for AND-of-operands), and OR (for carry-out aggregation). Different bit positions can't share these because they operate on different inputs.