2-Bit Full Adder Chain Circuit Simulator

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学べること

Chain full-adders to add multi-bit numbers.
Trace the carry path from one stage to the next.
Recognise that bit 0's carry-in being tied to 0 makes the first full-adder behave like a half-adder.
Understand why ripple-carry's serial carry chain limits speed for wide adders.
See how the same chained-full-adder structure scales to 32-, 64-, or arbitrary-bit addition.

仕組み

This is the textbook ripple-carry adder in its simplest form: two full-adders chained in series, with the carry-out of the first feeding the carry-in of the second. Unlike the half-adder + full-adder pattern, here both stages are full-adders — the bit-0 stage just has its carry-in tied to 0.

For each bit i, a full-adder computes: - Sum: Si = Ai ⊕ Bi ⊕ Cin - Carry-out: Couti = (Ai · Bi) + (Cin · (Ai ⊕ Bi))

The two full-adders process bits 0 and 1 of the operands. The final result is a 3-bit number (Cout1, S1, S0) representing the sum 0–6.

Why use two full-adders instead of a half + full? Two reasons: (1) uniformity — every stage is identical, simpler to scale to 32 or 64 bits; (2) carry-in support — if you ever want to add an external carry-in (for multi-precision arithmetic where the sum continues from a previous chunk), the full-adder at bit 0 already accommodates it.

For this 2-bit adder, the carry from bit 0 to bit 1 is the critical path. Bit 1 cannot finish computing its sum until bit 0's carry has propagated. With wide adders this serial dependency limits speed.

真理値表

Two 2-bit operands (A1A0 + B1B0) producing a 3-bit sum (Cout S1 S0). Showing representative rows from the full 16-row truth table.

入力				出力
A1	A0	B1	B0	Cout	S1	S0
0	0	0	0	0	0	0	0 + 0 = 0
0	1	0	0	0	0	1	1 + 0 = 1
0	1	0	1	0	1	0	1 + 1 = 2 (carry from bit 0 to bit 1)
1	1	0	1	1	0	0	3 + 1 = 4 (carry ripples to Cout)
1	0	1	0	1	0	0	2 + 2 = 4
1	1	1	1	1	1	0	3 + 3 = 6 (maximum)

ブール式

S_i = A_i \oplus B_i \oplus C_{in,i}

Per-stage sum bit — XOR of the two operand bits and the carry-in.

C_{out,i} = (A_i \cdot B_i) + (C_{in,i} \cdot (A_i \oplus B_i))

Per-stage carry-out — there's a carry if both bits are 1, or if either bit is 1 and the carry was already coming in.

C_{in,1} = C_{out,0}

Inter-stage wire: bit 1's carry-in equals bit 0's carry-out. This is the ripple chain.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

A1 = 0 A0 = 1 B1 = 0 B0 = 1

期待値: Cout S1 S0 = 010

観察ポイント: 1 + 1 = 2. Bit 0 generates a carry that propagates to bit 1, making S1 = 1.
2

A1 = 1 A0 = 0 B1 = 0 B0 = 1

期待値: Cout S1 S0 = 011

観察ポイント: 2 + 1 = 3. No carry from bit 0; bit 1's full-adder handles the high bit.
3

A1 = 1 A0 = 1 B1 = 0 B0 = 1

期待値: Cout S1 S0 = 100

観察ポイント: 3 + 1 = 4. Carry ripples from bit 0 → bit 1 → Cout. The longest carry chain in this 2-bit adder.
4

A1 = 1 A0 = 1 B1 = 1 B0 = 1

期待値: Cout S1 S0 = 110

観察ポイント: 3 + 3 = 6 — maximum sum. Both stages generate carries; output uses all three bits.

使用コンポーネント

実世界での応用

CPU integer ALU. Modern processors use 32 or 64 chained full-adders for their main arithmetic, often with carry-lookahead acceleration for speed.

Multi-precision arithmetic. Adding 256-bit numbers on a 64-bit CPU is done by chaining four 64-bit additions, each using the previous chunk's carry-out as the next chunk's carry-in.

Counter logic. A binary counter is just an adder that adds 1 each clock — exactly the same chained full-adder structure with B fixed to 0...01.

Address generators. Memory address calculations (base + offset) are wide additions, almost always implemented with chained full-adders.

Carry-save adders in multipliers. Multiplier circuits accumulate partial products using arrays of full-adders that delay the carry propagation, finishing with a single ripple-carry stage at the end.

よくある質問

Is this faster or slower than the half-adder + full-adder version?

Identical functionality and similar speed for 2 bits. The full-adder at bit 0 has its carry-in stuck at 0, so it effectively behaves as a half-adder. Slightly more transistors but no extra delay.

What's the worst-case delay through this 2-bit adder?

Two full-adder delays in series (bit 0 must finish before bit 1 can compute its sum). Each full-adder has ~3 gate delays internally, so worst-case ~6 gate delays for 2 bits.

Why is ripple-carry the standard introduction even though it's slow?

It's the most direct hardware translation of grade-school addition: add a column, carry to the next. Conceptual clarity matters more than speed in introductory material; carry-lookahead and Kogge-Stone come later as optimizations.

How do I do subtraction with this circuit?

Two's complement: feed B inverted, set bit 0's carry-in to 1, and the same chain computes A − B. Real ALUs add a row of XOR gates on the B inputs controlled by an add/subtract signal.

What changes for 32-bit ripple-carry?

Just more full-adders chained the same way. Worst-case delay scales linearly: 32 full-adders means ~32× the carry-propagation time of the slowest stage. This is why production CPUs use carry-lookahead instead.