RAM with Address Control Circuit Simulator

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学べること

Decompose a RAM into address decoder + word registers + output MUX.
Recognize that address bits drive both write-enable decoding and read-out selection.
Calculate the components for an N-word RAM: log₂N-bit address, N-output decoder, N-to-1 read MUX.
Apply this structure to register files and FIFOs.
Compare gate-level RAM with monolithic RAM blocks (dense but opaque).

仕組み

This circuit shows a RAM with explicit address control, exposing the address decoder and the read/write multiplexer that are usually hidden inside the RAM block. The decoder converts a binary address into one-hot word-select lines; the write path gates write-enable per-word; the read path uses an output MUX to route the selected word's data out.

For a 4-word, 4-bit RAM: - 2-bit address → 2-to-4 decoder → 4 word-select lines. - Each word is a 4-bit register with its own write-enable (decoder output AND global WE). - Output MUX is a 4-to-1 (per bit) controlled by the same address.

This decomposition makes the address-decoded write and address-driven read patterns explicit, helping you see why scaling to N words requires log₂(N)-bit addresses, an N-output decoder, and an N-to-1 output MUX (per bit).

Real RAM blocks bury these details in dedicated array structures (sense amplifiers, bit lines, row drivers), but the logical model is the same: address selects, data flows.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

Addr = 00 DataIn = 1010 WE = 1 Clock = rising

期待値: RAM[0] = 1010

観察ポイント: Decoder asserts word-0 select; combined with WE, word 0's flip-flops capture 1010.
2

Addr = 01 WE = 0

期待値: DataOut = (whatever word 1 holds)

観察ポイント: Decoder asserts word-1 select; output MUX routes word 1 to DataOut. WE low so no write.
3

Addr = 10 DataIn = 0011 WE = 1 Clock = rising

期待値: RAM[2] = 0011

観察ポイント: Different address — decoder picks word 2 — write 0011. Each address writes a separate word.
4

Addr = 00 WE = 0

期待値: DataOut = 1010

観察ポイント: Read address 0 — output reflects what was stored earlier. The previously written value is preserved.

使用コンポーネント

実世界での応用

CPU register file. A 32-register file is essentially this circuit at 32 words: 5-bit address, 5-to-32 decoder, 32 4-bit registers, 32-to-1 output MUX (per bit).

Custom block-RAM design in ASICs. Logic designers building specialized RAMs (e.g., dual-port FIFOs) start from this address-decoded structure.

Educational comparison with monolithic RAM blocks. Seeing the address decoder and MUX explicit makes it easier to understand why block RAMs have specific address widths and access patterns.

FIFO buffer cells. Each FIFO entry is a register; the head and tail pointers' decoded outputs gate read/write to specific entries.

Configurable address-mapped peripherals. Each peripheral register is an addressable cell; the bus address decoder routes reads and writes to the correct register.

よくある質問

Why expose the decoder when the RAM block hides it?

Educational clarity. Seeing the decoder explicit makes it obvious why N words need log₂N-bit addresses, and why the address fans out to one decoder + one output MUX. Production RAM blocks bury this detail for density, but the underlying structure is the same.

How does the read path get fast despite going through a MUX?

Real RAMs use sense amplifiers and tri-state output drivers instead of explicit MUXes. The bit line connects to all words; one word's select transistor activates, driving the bit line, which the sense amp then amplifies to the output. Faster than a logic-gate MUX of the same width.

Can I use one address for read and write simultaneously?

In a single-port RAM, no — read and write share the address bus. In a dual-port RAM, yes — separate read and write address buses each with their own decoder and MUX. CPU register files are typically dual-port (or multi-port) for simultaneous reads and writes.

What changes if I scale from 4 words to 1024 words?

Address width grows from 2 to 10 bits; decoder grows from 2-to-4 to 10-to-1024; word count grows from 4 to 1024; output MUX grows from 4-to-1 to 1024-to-1 per bit. All scale predictably with the address width.

How do real RAMs handle the access timing?

Multi-cycle access. The address propagates through the decoder (one delay), the word's data drives the bit line (another delay), the sense amp resolves (another delay), and the output emerges. Total RAS-to-output is typically 1–4 ns for SRAM, 30+ ns for DRAM.