4-Bit Binary Counter Circuit Simulator

インタラクティブシミュレーターには JavaScript が必要です

JavaScript を有効にするとライブ回路が読み込まれます。下の真理値表で動作を確認できます。

学べること

Build a 4-bit counter that increments by 1 each clock edge.
Cycle through 16 states from 0000 to 1111 then wrap.
Distinguish synchronous (all bits clock together) from asynchronous (ripple) counters.
Recognize that bit i toggles when all lower bits are 1.
Apply 4-bit counters to timers, address generators, and frequency dividers.

仕組み

A 4-bit binary counter counts clock pulses through values 0 to 15, incrementing by 1 each clock edge, then wrapping back to 0. The four flip-flops together hold the count; each new clock edge drives an adder (or toggle logic) that produces count+1.

In the synchronous form, all four flip-flops share the same clock — every bit updates simultaneously. The next-state logic for each bit i is: bit i toggles when all lower bits are 1 (i.e., AND of bits 0..i-1). This is the binary increment pattern.

In the asynchronous (ripple) form, each bit's toggle is clocked by the bit below it — simpler wiring but staggered timing.

The counter sequence: 0000 → 0001 → 0010 → ... → 1110 → 1111 → 0000 (wrap). One full cycle of bit 3 takes 16 clock pulses.

Counters are foundational to digital design — every timer, every program counter, every memory address generator is essentially a counter. Modern CPUs include dedicated counter cells in their standard libraries, often with parallel-load and reset for flexible initialization.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

1

Clock = running

期待値: Output cycles 0, 1, 2, ..., 15, 0, 1, ...

観察ポイント: Watch the binary lights and digit display. Each clock edge increments by 1; after 1111 (15) it wraps to 0000.
2

Clock = stopped at 0101

期待値: Counter holds at 5

観察ポイント: Stop the clock — counter freezes at whatever value it had. Sequential logic needs a clock to evolve.
3

Clock = after 8 edges

期待値: Bit 3 first lights up at the 8th edge

観察ポイント: Bit 3 (the MSB) only goes high when the count reaches 8 — the upper-half threshold.
4

Clock = after 16 edges

期待値: Counter wraps to 0000

観察ポイント: 16 edges complete one full cycle. The counter rolls over from 1111 to 0000 with no special intervention.

使用コンポーネント

実世界での応用

CPU program counter. The PC is essentially a counter that increments by the instruction width on each fetch.

Timer/counter peripherals. Microcontrollers have multiple hardware counters for precise timing of events, PWM generation, and pulse measurement.

Address generation in memory tests. ATE (test equipment) walks through memory addresses using a counter to write/read each cell during march tests.

Frequency divider chains. Cascading counters divide a master oscillator down to lower-frequency clocks for various subsystems.

Sequential state encoding. State machines with linearly progressing states often use a counter-based state register for simplicity.

よくある質問

What's the maximum count for a 4-bit counter?

1111 binary = 15 decimal. After that it wraps to 0000. For higher counts, use more bits: an 8-bit counter goes 0–255; a 16-bit counter goes 0–65535.

How is this different from a ripple counter?

A synchronous counter clocks all flip-flops together — bits update simultaneously on the clock edge. A ripple counter chains flip-flops; only bit 0 sees the master clock, and higher bits clock from lower bits' Q outputs. Synchronous is glitch-free but needs more logic; ripple is simpler but staggers.

Can I make it count up and down?

Yes — an up/down counter has a direction control input that switches between increment and decrement logic. Bit i's next state depends on whether direction is up (toggle when lower bits = 1) or down (toggle when lower bits = 0).

How do I reset the counter to 0?

Use the asynchronous reset input on each flip-flop, driven by an external reset signal. Setting reset high forces all bits to 0 instantly. Releasing reset lets the counter resume from 0 on the next clock edge.

How fast can a 4-bit counter run?

Synchronous counters are limited by the slowest combinational path between flip-flops. For a simple AND-tree increment, modern CMOS counters run at multi-GHz speeds. Wider counters add more logic depth and slow down accordingly.