学べること

  • Build a 3-input AND from two 2-input ANDs and verify the result.
  • Apply AND associativity: (A·B)·C = A·(B·C) regardless of grouping.
  • Read the 3-input AND truth table — exactly one of 8 rows produces 1.
  • Distinguish AND chaining (this circuit) from a single 3-input AND primitive.
  • Identify multi-factor authentication and safety interlocks as real AND applications.

仕組み

Three keys, one chest, one rule: every key must be turned for the chest to open. The circuit chains two 2-input AND gates to make a 3-input AND: (Key1 AND Key2) AND Key3. The output is high (chest open) only on the row where all three keys are 1.

This is the canonical example of AND chaining. Because AND is associative, you can build a 3-input AND from two 2-input ANDs in either order — (A AND B) AND C is identical to A AND (B AND C). Either way, the result is 1 only when every input is 1, and 0 otherwise.

With three inputs there are 2³ = 8 possible combinations. Exactly one row produces 1; the other 7 produce 0. This is the inverse pattern from a 3-input OR (where 7 rows produce 1 and only the all-zeros row produces 0).

The educational difference vs. the AND Gate Security System is the chained construction — even though digital simulators usually offer a single 3-input AND primitive, this circuit shows you how that primitive is internally built and why associativity guarantees correctness.

真理値表

Three keys, 8 combinations. Only the all-keys-turned row opens the chest.

入力 出力
Key1Key2Key3 Open
000 0 No keys turned
001 0
010 0
011 0
100 0
101 0
110 0 Two keys, but Key3 missing
111 1 All three turned — chest opens

ブール式

Y=ABCY = A \cdot B \cdot C

Standard 3-input AND — output is 1 only if every input is 1.

Y=(AB)CY = (A \cdot B) \cdot C

Same expression with explicit chaining of two 2-input ANDs.

Y=A(BC)Y = A \cdot (B \cdot C)

Equivalent grouping — associativity guarantees the same output.

順を追って試す

上の埋め込み回路で入力を設定し、期待される結果と一致するか確認しましょう。

  1. 1
    Key1 = 0 Key2 = 0 Key3 = 0
    期待値: Open = 0
    観察ポイント: All keys off — chest stays locked. The default state.
  2. 2
    Key1 = 1 Key2 = 1 Key3 = 0
    期待値: Open = 0
    観察ポイント: Two keys turned but Key3 still off. AND requires all-or-nothing — close isn't enough.
  3. 3
    Key1 = 1 Key2 = 1 Key3 = 1
    期待値: Open = 1
    観察ポイント: All three keys on — chest opens. The only winning combination.
  4. 4
    Key1 = 0 Key2 = 1 Key3 = 1
    期待値: Open = 0
    観察ポイント: Flip Key1 off and the chest re-locks immediately. Removing any single key drops the AND output to 0.

使用コンポーネント

実世界での応用

Multi-factor authentication. "Something you know, something you have, something you are" combines via AND: password AND key card AND fingerprint must all be valid. Each factor is a separate input that must be 1.

Industrial safety interlocks. A press machine requires guard closed AND emergency stop released AND two-hand-control buttons depressed. Removing any single condition stops the machine.

Memory write enable. A RAM cell writes only when chip-select AND write-enable AND row-strobe AND data-valid are all asserted. Wide ANDs gate sensitive operations.

Boolean SOP minterms. A Sum-of-Products expression is an OR of ANDed minterms. Each minterm — the AND of variables (or their inverses) — represents one specific combination. This 3-input AND on its own is a single minterm, lighting up exactly one row of the truth table.

Permission AND. "Allow this transaction if the user is logged in AND has admin privileges AND has confirmed via 2FA" — every condition must be true.

よくある質問

Why use two 2-input ANDs instead of one 3-input AND?
Educational clarity. Real chips offer 3-, 4-, even 8-input ANDs as single gates. But on the smallest CMOS standard cells, wider ANDs are often *implemented* as chained narrower gates. This circuit makes the chaining explicit.
Does the order of chaining matter?
No. (A AND B) AND C produces the same output as A AND (B AND C) — that's the associativity property. The simulator may show different gate placement but the truth table is identical.
What's the propagation delay through a chain of two ANDs?
About 2 gate delays (one per AND). For modern CMOS that's ~100–500 ps. Wider single ANDs have one gate delay but more transistors stacked, which can be slower in some processes — there's a real trade-off.
Can I extend this to a 4-key chest?
Yes — chain another AND. Either (((A·B)·C)·D), or ((A·B)·(C·D)), or any other associative grouping. All give the same result: output 1 only when every input is 1.
How does this relate to Sum-of-Products form?
Each ANDed term in SOP is called a "minterm" — exactly one row of the truth table where it's 1. This circuit IS a single minterm: A·B·C, true only on the (1,1,1) row. Real SOP expressions OR several minterms together to specify any Boolean function.

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