logic-gates
Multi-Input Logic Gates: From 3-Input AND to Beyond
TL;DR: A wide AND/OR/XOR gate can be built two ways: cascaded (linear delay, ) or as a balanced tree (logarithmic delay, ). Both use the same number of gates —...
cpu-architecture
Visualizing the Fetch-Decode-Execute Cycle in a Simulator
TL;DR: Every CPU executes instructions through a three-phase loop: fetch (read instruction from memory using the Program Counter), decode (the Control Unit interprets the opcode), and execute (the ALU and...
sequential-logic
Counters and State Machines: Controlling Digital Sequences
TL;DR: A counter is a sequential circuit that steps through a fixed binary sequence on each clock edge. A finite state machine (FSM) generalizes this with conditional transitions driven by...
combinational-logic
Decoders and Encoders: Driving a 7-Segment Display
TL;DR: A decoder converts an n-bit input into one of one-hot outputs. An encoder does the inverse. A BCD-to-7-segment decoder is a special case: it activates multiple outputs at once...
logic-notation
ANSI vs IEC Logic Symbols: A Schematic Reading Guide
TL;DR: ANSI/MIL-STD-806 gives each logic gate a distinctive shape (D for AND, shield for OR). IEC 60617 places every gate in a uniform rectangle and identifies the function with a...
education
Grading Circuits in Seconds: The DigiSim Workflow
TL;DR: Shareable DigiSim.io URLs replace breadboard photos and screenshots with circuits that the grader can actually run. Functional testing — toggling each input combination — takes seconds per submission, and...
frequency-division
Frequency Division: From Flip-Flops to Modulo-N Counters
TL;DR: Frequency division turns a fast clock into a slower one. A T flip-flop divides by 2; cascading of them divides by . For arbitrary ratios, a counter plus comparator...
sequential-logic
Mastering Sequential Logic: The D Latch Explained and Simulated
TL;DR: A D latch stores one bit. It has two inputs (Data and Enable) and follows the characteristic equation . When Enable is HIGH, the latch is transparent — Q...
combinational-logic
Multiplexers (MUX) Demystified: The Data Traffic Controller
TL;DR: A multiplexer (MUX) selects one of data inputs and routes it to a single output, controlled by select lines. The Boolean expression for a 4-to-1 MUX is . A...
sequential-logic
SR vs. JK Flip-Flops: The Basics of Sequential Logic
TL;DR: The SR latch is the simplest memory element but has a forbidden state when both inputs are 1. The JK flip-flop fixes this by redefining J=K=1 as a toggle,...
and-gate
The AND Gate: Foundation of Digital Logic and Decision Making
TL;DR: An AND gate outputs 1 only when every input is 1; otherwise the output is 0. Boolean expression . Despite the simple logic, real AND gates have non-zero propagation...
clock-signal
The Clock Pulse: Why Computers Need a Heartbeat
TL;DR: A clock signal is a periodic square wave (typically 50% duty cycle) that synchronizes every flip-flop and pipeline stage in a synchronous digital system. Modern CPUs derive multi-GHz clocks...
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