Clock Skew and Its Effect on Timing
TL;DR: Clock skew is the difference between clock-edge arrival times at a path's capture and launch registers. With the sign convention used here, positive skew gives a simple...
Tag
Sequential logic
A collection of 11 posts
From explanation to experiment
Sequential circuits depend on stored state as well as current inputs. Trace a short sequence of clock edges, record each state, and distinguish the simulator’s event model from the timing limits of a physical integrated circuit.
Mealy vs Moore State Machines: With Examples
TL;DR: A Moore machine's output is a function of current state; a Mealy machine's output is a function of current state and current input. Mealy modeling can respond within...
SISO, SIPO, PISO, PIPO: Shift Register Modes
TL;DR: A shift register is a chain of flip-flops with a shared clock. Pick where the data enters and exits — serially or in parallel — and you get four...
Counters and State Machines: Controlling Digital Sequences
TL;DR: A counter follows a defined state sequence; a finite-state machine (FSM) adds input-dependent transitions and outputs. Ripple-counter bits settle at different times. Synchronous counters and...
Mastering Sequential Logic: The D Latch Explained and Simulated
TL;DR: A D latch stores one bit and follows . When Enable is HIGH, Q follows D after propagation delay; when Enable is LOW, Q holds. Gating D and prevents...
SR vs. JK Flip-Flops: The Basics of Sequential Logic
TL;DR: The SR latch is the simplest memory element but has a forbidden state when both inputs are 1. The JK flip-flop fixes this by redefining J=K...
The D Flip-Flop: Edge-Triggered Memory in Digital Design
TL;DR: A D flip-flop samples its data (D) input at an active clock edge, updates Q after its clock-to-Q delay, and holds that value until the...
The JK Flip-Flop: Universal Sequential Building Block
TL;DR: On its active clock edge, a JK flip-flop holds for JK=00, resets for 01, sets for 10, and toggles for 11. Its next-state equation is...
The Johnson Counter: A Twisted-Ring Counter Explained
TL;DR: An -stage Johnson counter is a shift register whose inverted last output feeds the first input. From a valid initial state it traverses states: ones fill the register...
The T Flip-Flop: A Toggle Cell for Counters and Timers
TL;DR: A T flip-flop toggles its stored bit on every active clock edge when T=1 and holds it when T=0. Its characteristic equation is . Tied permanently...
The SR Latch: Cross-Coupled NOR and NAND Forms
TL;DR: The SR (Set–Reset) latch is a bistable circuit built from cross-coupled NOR gates (active-high) or NAND gates (active-low). It supports Set, Reset, and Hold...