Intel 4004-Inspired CPU: A Transparent 4-Bit Teaching Model
TL;DR: This is a working 4-bit teaching CPU inspired by the Intel 4004, not an emulator or transistor-level reconstruction. It uses a custom instruction set, unified memory...
Tag
CPU architecture
A collection of 14 posts
Build a CPU from Scratch in a Simulator
TL;DR: This guide defines one complete teaching architecture before drawing wires: an 8-bit data path and address space, byte-wide unified RAM, 16-bit instructions fetched as two...
CPU Flags Register: Carry, Zero, Overflow, Sign
TL;DR: Z, N, C, and V are not four interchangeable kinds of “overflow.” Z and N describe the truncated result, C describes unsigned carry, and V describes signed overflow...
Demultiplexer Tutorial: 1-to-4 and 1-to-8 (DEMUX)
TL;DR: A demultiplexer (DEMUX) is a combinational circuit that takes one data input and routes it to one of output lines, with the destination chosen by an n-bit...
Endianness: Big vs Little (with Bus Diagrams)
TL;DR: Endianness is the convention for how a multi-byte value is laid out in memory. Big-endian stores the most-significant byte at the lowest address, as do...
How a Microprocessor Works: Fetch-Decode-Execute Deep Dive
TL;DR: Fetch, decode, and execute form a useful conceptual model for an instruction processor: choose an instruction address, obtain and interpret the instruction, perform its operation, and establish the...
How an ALU Works: Arithmetic Logic Unit from Gates
TL;DR: A small ALU is a combinational datapath: candidate arithmetic, logic, and shift functions operate on the same input words, and a multiplexer selects the visible result. The design...
Instruction Register and the Decode Stage
TL;DR: In a simple CPU, an instruction register (IR) captures a fetched instruction so decode sees stable bits. Decode identifies the instruction format, extracts register and immediate fields, checks...
Program Counter Explained: The CPU's Bookmark
TL;DR: The program counter (PC), also called the instruction pointer in some architectures, identifies the next instruction to fetch. Sequential execution advances it by the decoded instruction length; branches...
RAM vs ROM: The Essential Difference (with Circuits)
TL;DR: In an introductory computer, RAM is writable working storage and ROM supplies fixed instructions or constants. Physical technology adds important nuance: SRAM and DRAM are usually volatile, while...
Tri-State Buffers and Bus Arbitration Explained
TL;DR: An enabled tri-state buffer drives 0 or 1; when disabled, it presents high impedance (Hi-Z). Z is an electrical drive state, not a third Boolean value...
Two's Complement: Signed Binary Arithmetic Explained
TL;DR: Two's complement is the dominant encoding for fixed-width signed integers. The most significant bit has weight and the lower bits keep their positive weights. It has one...