RAM
Use DigiSim's fixed 256 × 8 RAM with rising-edge synchronous writes, asynchronous reads, and tri-state Q0–Q7. CS, WE, and OE are active HIGH.
Overview
DigiSim RAM is a fixed 256-byte × 8-bit memory with synchronous writes, asynchronous reads, tri-state outputs, and a live memory inspector.
Exact DigiSim.io Implementation
| Pin | Role |
|---|---|
| A0–A7 | Address 0x00–0xFF; A0 is LSB. |
| D0–D7 | Write data; D0 is LSB. |
| CS, WE, OE | All controls are active HIGH. |
| CLK | Rising-edge write clock. |
| Q0–Q7 | Read data or high-impedance. |
Inspector Window
- Click/open the RAM to use the draggable 256 × 8 Memory Viewer.
- Hex View shows a 16 × 16 byte table plus ASCII; click a byte to edit it.
- Bit Grid exposes all eight bits of every byte; click a bit to toggle it.
- The header shows read/write counts, non-zero bytes or set bits, last access, and last-write highlighting.
- Import, export, and clear actions modify the live RAM image.
Learning Path
Prerequisites
Next Steps
Frequently Asked Questions
What is RAM?
With CS=1 and WE=1, a rising CLK edge stores D0–D7 at address A0–A7. With CS=1, WE=0, and OE=1, Q0–Q7 asynchronously present the addressed byte; otherwise the outputs are Z.
How does RAM addressing work?
A0–A7 select one of 256 byte locations, 0x00–0xFF, with A0 as the least-significant address bit. This is simulator state; the component does not model a specific SRAM or DRAM cell technology.