Static vs Dynamic Hazards in Combinational Logic

TL;DR: A static hazard is a possible pulse on an output that should remain constant during an input transition; a dynamic hazard produces several output transitions where one was intended. For a two-level SOP network under a single-input-change assumption, cover every adjacent pair of 1-cells with a common implicant; the added consensus term preserves the Boolean function while closing the hazardous handoff. That proof does not automatically cover multiple changing inputs, multilevel mapping, asynchronous feedback, or synthesis that removes the redundant logic.

A truth table specifies stable input/output values. It does not specify what happens while signals travel through gates with different delays. Two implementations of the same Boolean function can therefore agree at every stable row and behave differently for a few nanoseconds after an input change.

That transient behavior matters when it reaches an asynchronous control, a clock or reset input, an external pin, a level-sensitive state element, or a sampling edge.

Hazard, Glitch, and Race

A race exists when two or more relevant signal paths compete in time. A hazard is a circuit structure and transition for which some allowed path-delay ordering can produce an unwanted output transition. A glitch is the pulse observed in one actual timing case.

The distinction is useful:

• zero-delay simulation can hide a hazard;
• one set of delays may contain the hazard but show no pulse;
• process, voltage, temperature, placement, or routing can change which path wins; and
• “I did not see a glitch” is not a proof of hazard freedom.

Static Hazards

A static-1 hazard is possible when the output should remain 1 but can briefly fall to 0. It is commonly analyzed in a two-level sum-of-products (SOP) network.

A static-0 hazard is the dual: the output should remain 0 but can briefly rise to 1. It is commonly analyzed in a two-level product-of-sums (POS) network.

The textbook K-map procedure assumes:

1. the network is implemented in the stated two-level form;
2. one input variable changes at a time;
3. gates and interconnect may have arbitrary positive delays; and
4. stable input values satisfy the intended Boolean function.

Change those assumptions and the proof must change too.

Worked Static-1 Example

Consider:

When $B=C=1$, the stable output is 1 for either value of $A$:

• at $A=1$, term $AB$ holds the OR output high;
• at $A=0$, term $\overline{A}C$ holds it high.

During a 1-to-0 transition on $A$, the direct path can disable $AB$ before the inverter path enables $\overline{A}C$:

The middle row is not another truth-table input. It represents unequal arrival times inside the implementation.

Find the Seam on a Karnaugh Map

For variables $A$, $B$, and $C$:

              BC
        00   01   11   10
      +----+----+----+----+
 A=0  |  0 |  1 |  1 |  0 |
      +----+----+----+----+
 A=1  |  0 |  0 |  1 |  1 |
      +----+----+----+----+

The original SOP uses:

• $\overline{A}C$ for the top-row cells where $C=1$; and
• $AB$ for the bottom-row cells where $B=1$.

The cells A=0, B=1, C=1 and A=1, B=1, C=1 are adjacent because only A differs. Yet no selected implicant covers both. The output responsibility must transfer from one product term to another when A changes. That uncovered adjacency is the static-1 seam.

Add the Consensus Term

The consensus of $AB$ and $\overline{A}C$ is $BC$:

The consensus theorem gives:

so the added term does not change any stable truth-table result. During the hazardous transition with $B=C=1$, however, $BC$ remains 1 and holds the OR output high.

On the K-map, $BC$ is the vertical group spanning the two adjacent cells. The general two-level SOP procedure is:

1. identify every permitted single-variable transition between adjacent 1-cells;
2. check whether the implemented cover contains an implicant spanning each pair;
3. add an appropriate consensus/cover term for any uncovered pair; and
4. verify that synthesis and physical implementation preserve the intended structure.

The dual procedure covers adjacent 0-cells in a POS implementation to prevent static-0 hazards.

Minimal Logic and Hazard-Free Logic Optimize Different Objectives

The minimal SOP has fewer terms because $BC$ is Boolean-redundant. The hazard-free SOP deliberately retains physical redundancy.

That creates an implementation issue: a logic synthesizer is normally allowed to remove terms that do not change the Boolean function. It may also factor the expression into a multilevel network or map it into lookup tables and cells with different internal behavior.

If hazard freedom is a requirement:

• express it as an implementation constraint, not a comment;
• use the vendor’s documented preservation or hazard-free methodology;
• inspect the synthesized netlist;
• perform timing-aware verification on the mapped design; and
• validate the final routed implementation where the target flow supports it.

An RTL equation alone does not guarantee the physical consensus path survives optimization.

Dynamic Hazards

A dynamic hazard occurs when the correct output should change once but the implementation can change it several times before settling—for example, 0 → 1 → 0 → 1.

Dynamic hazards require multiple interacting delays and are associated with multilevel, reconvergent logic. A two-level network proven free of the relevant static hazards under the single-input-change model is easier to reason about; a factored or technology-mapped realization may no longer have that structure.

There is no universal “add one term” correction for an arbitrary dynamic hazard. Practical responses include:

• redesigning or resynthesizing into a form with a hazard-free proof;
• registering the result before it reaches a sensitive consumer;
• using a handshake or state-machine style designed for asynchronous operation;
• applying target-specific glitch-free mux/clock-control cells; and
• verifying the implemented delay behavior.

Adding arbitrary delay buffers to “balance” paths is brittle across process, voltage, temperature, and routing unless the design methodology explicitly relies on bounded delays and constrains them.

Multiple Input Changes and Functional Hazards

K-map adjacency represents one variable changing. If two independent inputs can change close together, the circuit can pass through one of several intermediate stable combinations. Even a network that is free of single-input static hazards can produce a functional hazard.

For example, a transition from 00 to 11 might physically pass through 01 or 10. If the Boolean function differs at those intermediate rows, no redundant gate can make both paths equivalent without changing the function.

System-level options include:

• enforce a single-input-change protocol;
• encode transitions so only one bit changes, where appropriate;
• synchronize and register related controls;
• use request/acknowledge handshakes;
• capture a coherent data bundle only after a valid signal; or
• redesign the interface so simultaneous input changes are not interpreted combinationally.

Gray code helps with a specific adjacent-state problem; it is not a general cure for arbitrary buses.

When Synchronous Logic Contains the Glitch

If a combinational result feeds only a flip-flop D input, and the network has settled with setup margin before the sampling edge and remains stable through hold time, an internal glitch need not become architectural state.

That statement has limits:

• the glitch still consumes dynamic power;
• it may propagate into another path with different timing;
• it is dangerous on asynchronous resets, sets, clocks, enables, and handshakes;
• it may be captured when timing margin shrinks; and
• it can be externally visible on pins or chip-select signals.

Do not generate a clock by passing logic through an ordinary combinational network. Use integrated clock-gating cells, FPGA clock-control resources, or an enable-based synchronous design.

Asynchronous and Essential Hazards

Asynchronous sequential circuits intentionally allow transitions to influence state without a global sampling edge. They require a design methodology whose delay assumptions, state encoding, handshakes, and hazard-freedom conditions are explicit.

An essential hazard is associated with unequal propagation of an input through an asynchronous feedback implementation such that internal state can advance before the input change has reached every required point. It is not simply another name for a combinational static glitch, and a consensus term does not generally remove it.

Essential-hazard treatment belongs to the specification and implementation of the asynchronous machine—often involving feedback-delay assumptions or a different circuit structure. Switching to synchronous logic is one option, not a proof that all hazards disappear.

Simulate the Right Model

A zero-delay digital simulator usually changes all dependent nodes within the same simulated instant and may show no pulse. To study hazards, the model must include unequal propagation:

1. build $F=AB+\overline{A}C$;
2. hold $B=C=1$;
3. assign or introduce a documented delay difference between the direct and inverted A paths;
4. toggle only A;
5. inspect F at a time resolution smaller than the modeled delay; and
6. add $BC$ and repeat.

If the simulator’s buffer component has zero logical delay, chaining buffers proves nothing. Use a delay-aware feature, gate-level timing simulation, or a physical measurement.

The absence of a pulse in one delay assignment is evidence for that run, not a proof for every allowed delay.

Verification Checklist

• Which inputs are permitted to change together?
• Must the output stay constant or make one transition?
• Is the implemented network two-level, factored, or LUT/cell mapped?
• Does every relevant adjacent K-map pair share a cover term?
• Can synthesis remove or refactor the redundancy?
• Does the output drive only a registered D input, or a sensitive control?
• Have minimum and maximum delays been checked after mapping and routing?
• Are asynchronous feedback and essential hazards handled by a recognized methodology?

Next Steps

The clock-skew guide explains how unequal clock arrival changes setup and hold margins. Don’t-care conditions in Karnaugh maps explains when unspecified input combinations can aid minimization—but a don’t-care must be justified by the system contract before it is used in a hazard analysis.

Primary Reference

• David A. Huffman, “The Design and Use of Hazard-Free Switching Networks,” Journal of the ACM, 1957