BCD to 7-Segment Decoder: From Numbers to Display

TL;DR: A BCD to 7-segment decoder takes a 4-bit binary-coded-decimal digit (0–9) and lights the right combination of segments a–g on a digital display. The mapping is defined by a 10-row truth table; each segment’s boolean expression is derived from the table and minimized using K-maps, then implemented in a chip like the 74LS47 (common anode) or 74LS48 (common cathode).

Seven-segment displays appear in clocks, appliances, calculators, scoreboards, and instruments. When a system supplies a BCD digit rather than seven individual segment signals, a combinational decoder converts the 4-bit code into the required pattern. That decoder is a clear practical application of Boolean algebra and Karnaugh maps.

This post defines BCD, lays out the segment-naming convention, builds the truth table, derives the boolean equations for each segment, contrasts common-anode with common-cathode wiring, and points to the 74LS47 / 74LS48 chips that implement the whole thing. The simulator templates referenced at the end let you wire one up by hand.

What Is BCD?

BCD — Binary-Coded Decimal — is an encoding that uses 4 bits to represent each decimal digit 0 through 9. Unlike straight binary, BCD wastes the codes 1010 through 1111 (decimal 10–15): they are simply not used.

The convention used in this post: A is the most-significant bit, D is the least. Some textbooks use the opposite order; the equations are identical with relabeling.

Why BCD instead of straight binary? Decimal digits map directly to digit-oriented displays, and a fixed-scale decimal quantity can preserve stored decimal digits without binary-fraction conversion. Arithmetic is exact only while the mathematical result fits the chosen digit count and scale; division and other non-terminating results still need a rounding rule.

The storage comparison needs a denominator. BCD uses 4 bits per decimal digit, while the information content of ten symbols is $\log_2 10\approx3.322$ bits. About 16.9% of each BCD nibble’s theoretical code space is unused; equivalently, 4 bits is about 20.4% more than $\log_2 10$. For a particular bounded integer range, compare the actual binary and BCD widths rather than applying one percentage blindly.

The six unused codes—1010 through 1111—may become don’t-care entries when minimizing the segment equations, but only if the system guarantees that their displayed outputs are irrelevant. If an invalid code can occur during reset, a bus transition, or a fault, assign it a deliberate blank or error pattern instead. A don’t-care is a design permission, not a claim that hardware can never present the input.

The Seven Segments

A standard 7-segment display has seven LEDs arranged like an 8, conventionally labeled a through g:

   ┌─── a ───┐
   │         │
   f         b
   │         │
   ├─── g ───┤
   │         │
   e         c
   │         │
   └─── d ───┘

• a is the top horizontal bar.
• b is the upper-right vertical.
• c is the lower-right vertical.
• d is the bottom horizontal.
• e is the lower-left vertical.
• f is the upper-left vertical.
• g is the middle horizontal.

A decimal digit lights a specific subset:

DigiSim’s SEVEN_SEGMENT_DISPLAY component takes seven inputs in this exact order; the DIGIT_DISPLAY is a higher-level abstraction that takes the 4-bit BCD input directly and handles decoding internally.

The Full Truth Table

Combining the BCD encoding with the segment mapping gives one table with 16 rows (10 valid + 6 don’t-cares) and 7 segment columns:

The table assumes active-high logical segment commands—a 1 means “request this segment on.” A common-cathode driver can often use that polarity, while a common-anode driver commonly uses active-low outputs. Physical driver stages also differ in current direction, voltage drop, and output structure; the distinction is not merely a schematic inverter.

Deriving the Segment Equations

Each segment column above is one Boolean function of four inputs. With 6 don’t-care rows, the K-map minimization gives much shorter expressions than a naive sum-of-products. The technique is the Sum of Products method with K-map reduction.

Segment a

Segment a is on for digits 0, 2, 3, 5, 6, 7, 8, 9 — and off for 1, 4. With the don’t-cares treated optimally, K-map minimization gives:

$a = A + C + B \cdot D + \overline{B} \cdot \overline{D}$

(Here $\overline{B}$ means NOT B; some books write it $B'$.) The term $\overline{B} \cdot \overline{D}$ — both B and D are zero — covers the 0 and 2 cases efficiently; $B \cdot D$ — both ones — covers 3, 5, 7, 9; $A$ alone covers 8 and 9 (and the don’t-cares 10–15); $C$ alone covers 2, 3, 6, 7.

This expression uses one AND per product term and an OR reduction. Exact cell or transistor count depends on the logic family, complemented-signal availability, and synthesis mapping.

Segment b

Segment b is on for 0, 1, 2, 3, 4, 7, 8, 9 — off for 5, 6. K-map gives:

$b = \overline{B} + \overline{C} \cdot \overline{D} + C \cdot D$

Segment c

Segment c is on for 0, 1, 3, 4, 5, 6, 7, 8, 9 — off only for 2. K-map gives:

$c = B + \overline{C} + D$

This is the simplest of all — only three terms because there is only one zero-output row and the don’t-cares fill the rest of the map.

Segment d

Segment d is on for 0, 2, 3, 5, 6, 8, 9 — off for 1, 4, 7. K-map gives:

$d = \overline{B} \cdot \overline{D} + C \cdot \overline{D} + B \cdot \overline{C} \cdot D + \overline{B} \cdot C + A$

Segment e

Segment e is on for 0, 2, 6, 8 — off for 1, 3, 4, 5, 7, 9. K-map gives:

$e = \overline{B} \cdot \overline{D} + C \cdot \overline{D}$

Note both terms share $\overline{D}$—equivalently $e=\overline{D}(\overline{B}+C)$. Even digits are necessary for e under this input convention, but not sufficient: digit 4 has $D=0$ while e remains off. The factored form can use one OR followed by one AND, plus whatever inversion is needed.

Segment f

Segment f is on for 0, 4, 5, 6, 8, 9 — off for 1, 2, 3, 7. K-map gives:

$f = A + B \cdot \overline{C} + \overline{C} \cdot \overline{D} + B \cdot \overline{D}$

Segment g

Segment g — the middle bar — is on for 2, 3, 4, 5, 6, 8, 9 — off for 0, 1, 7. K-map gives:

$g = A + B \cdot \overline{C} + C \cdot \overline{D} + \overline{B} \cdot C$

These expressions are one valid minimization under the stated active-high and don’t-care assumptions. Equivalent minimum forms can look different, and a commercial decoder’s internal network need not match this textbook sum of products.

Common Anode vs Common Cathode

The 7-segment display itself comes in two physical wirings. They differ in which side of every LED is shared with a single common pin.

Common Cathode

All seven LED cathodes (negative terminals) are tied together to a single common pin connected to ground. Each anode is driven separately. To light a segment, drive its anode high.

• Driver output: active-high — 1 lights the segment.
• Truth table interpretation: matches the table above directly.
• Companion chip: 74LS48 — outputs are active-high.

Common Anode

All seven LED anodes are tied together to a single common pin connected to V_CC. Each cathode is driven separately. To light a segment, pull its cathode low.

• Driver output: active-low — 0 lights the segment.
• Truth table interpretation: invert every output column.
• Companion chip: 74LS47 — outputs are active-low (open-collector).

At the Boolean level, changing polarity can be represented by output inversion. In physical hardware, choose a driver that can source or sink the required current and place a current-limiting element in each illuminated segment path. Never connect an LED segment to an unrestricted voltage source.

The 74LS47 and 74LS48

The 74LS47 and 74LS48 are TTL BCD-to-seven-segment decoder/driver functions. They are useful references, but select and wire an exact orderable device from its data sheet rather than treating the names as polarity-only drop-in abstractions.

The classic device notation normally labels A as the least-significant BCD input and D as the most significant. This article chose A as MSB and D as LSB in its equations. Relabel the variables before copying an equation into a 74LS47/48 pin-level design.

Both chips also include three useful auxiliary inputs:

• LT (Lamp Test): Pulled low to force all seven outputs on, regardless of the BCD input. Used to verify every LED is functional.
• RBI (Ripple Blanking Input): Pulled low along with BCD input 0000 to blank the display instead of showing 0. Used to suppress leading zeros in multi-digit displays — 00073 becomes 73.
• BI/RBO (Blanking Input / Ripple Blanking Output): A dual-function pin used for overriding blanking and ripple-blanking chains. Its behavior depends on the other control inputs; follow the device function table rather than treating it as an ordinary bidirectional logic pin.

Together those three pins enable cascading multiple decoder/display pairs into a multi-digit numeric display where leading zeros automatically vanish.

The behavior for invalid BCD inputs (1010–1111) is chip-defined and produces idiosyncratic non-digit segment patterns — useful as a debugging signal but not portable.

Real-World Applications

BCD-to-seven-segment decoding is common in devices with numeric displays:

• Digital clocks — counters or stored time digits feed combinational segment generation, often through a multiplexed driver. Seconds and minutes require modulo-60 behavior, commonly decomposed into units and tens digits.
• Calculators and meters — several digits may share segment drive through multiplexing. The controller selects one digit and its segment pattern at a time. Refresh rate, peak current, duty cycle, brightness, and ghosting must be designed together.
• Multi-digit voltmeters and frequency counters — a counter feeds a BCD-encoded register, the register feeds the decoder, and the decoder lights the segments.
• Score boards and odometers — same multiplexing trick, often with brighter LED arrays.

Build It in DigiSim

Open the DECODER component to see the general-purpose decoder building block. For the BCD-to-7-segment specific case, drop a DIGIT_DISPLAY — which has the conversion baked in — or build the decoder by hand and feed the seven outputs to a SEVEN_SEGMENT_DISPLAY.

Wire four input switches as A, B, C, D (most significant to least). Implement segment a first using the equation above:

1. Two AND gates: one for $B \cdot D$, one for $\overline{B} \cdot \overline{D}$.
2. One 4-input OR combining $A$, $C$, and the two AND outputs.

Toggle the switches through the BCD codes 0–9 and verify segment a lights in the correct cases. Then add segments b through g following the equations above.

Finally, test codes 10–15. If they were used as don’t-cares, record the actual patterns and confirm that upstream logic prevents them whenever the display is visible. For a fault-indicating design, replace the don’t-cares with a defined blank or error glyph and re-minimize.

The next post in the combinational track — BCD: Binary-Coded Decimal Fundamentals — covers BCD addition, the add-6 correction after an invalid digit or decimal carry, and packed vs unpacked BCD storage. Read alongside Decoders and Encoders Driving a 7-Segment Display for the broader story of how a few binary inputs select one display pattern out of many.

Reference

• Texas Instruments SN74LS47 family BCD-to-seven-segment decoder/driver data sheet