4-to-1 Multiplexer Circuit Simulator

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Activa JavaScript para cargar el circuito en vivo. La tabla de verdad de abajo describe el comportamiento del circuito.

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Lo que aprenderás

Use a 2-bit select code to choose among 4 data inputs.
Read the 4-to-1 MUX truth table.
Write the SOP Boolean expression with four select-decode AND terms.
Build a 4-to-1 MUX from a tree of 2-to-1 MUXes.
Apply 4-to-1 MUXes for ALU op selection, register reads, and FPGA LUTs.

Cómo funciona

A 4-to-1 multiplexer routes one of four data inputs (D0–D3) to a single output (Y), controlled by a 2-bit select code (S1, S0). The 2-bit select addresses 4 inputs because 2² = 4.

Select mapping: - S1S0 = 00 → Y = D0 - S1S0 = 01 → Y = D1 - S1S0 = 10 → Y = D2 - S1S0 = 11 → Y = D3

The Boolean expression is a sum of four AND-terms, each AND'ing the data input with the matching select decode: Y = ¬S1·¬S0·D0 + ¬S1·S0·D1 + S1·¬S0·D2 + S1·S0·D3.

A 4-to-1 MUX can be built as a tree of three 2-to-1 MUXes: two MUXes pair (D0,D1) and (D2,D3) using S0 as their select; a third 2-to-1 chooses between those two pair-results using S1. This decomposition generalises: an N-to-1 MUX is a binary tree of (N−1) 2-to-1 MUXes.

When used to implement arbitrary 2-input Boolean functions, a 4-to-1 MUX with the function's truth-table values wired to D0–D3 and the function's variables on S1, S0 reproduces any Boolean function of those variables. This is the lookup-table principle that FPGAs use everywhere.

Tabla de verdad

Select code S1S0 chooses one of D0..D3 to route to Y. Showing each select case with its routed value.

Entradas			Salida
S1	S0	Selected	Y
0	0	0	0	S1S0=00 → Y = D0 (=0 here)
0	0	1	1	S1S0=00 → Y = D0 (=1)
0	1	0	0	S1S0=01 → Y = D1 (=0)
0	1	1	1	S1S0=01 → Y = D1 (=1)
1	0	0	0	S1S0=10 → Y = D2
1	0	1	1
1	1	0	0	S1S0=11 → Y = D3
1	1	1	1

Expresión booleana

Y = \overline{S_1}\overline{S_0}D_0 + \overline{S_1}S_0 D_1 + S_1\overline{S_0}D_2 + S_1 S_0 D_3

Sum-of-products form — four AND terms, each gated by a different select-code minterm.

Pruébalo paso a paso

Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.

1

S1 = 0 S0 = 0 D0 = 1

Esperado: Y = 1

Lo que verás: Select=00 routes D0. Set D0=1, the other Ds don't matter.
2

S1 = 0 S0 = 1 D1 = 1

Esperado: Y = 1

Lo que verás: Select=01 routes D1. Flipping S0 has selected a different data input.
3

S1 = 1 S0 = 0 D2 = 1

Esperado: Y = 1

Lo que verás: Select=10 routes D2. The high bit of select swaps to the upper half of the input bank.
4

S1 = 1 S0 = 1 D3 = 1

Esperado: Y = 1

Lo que verás: Select=11 routes D3 — the last input. Watching one D at a time, you can verify each row of the truth table.

Componentes utilizados

Aplicaciones en el mundo real

ALU operation selection. Choosing among add, subtract, AND, OR results: a 4-to-1 MUX with operation code as select.

Register file read ports. Reading one of 4 registers uses a 4-to-1 MUX with the register address as select.

FPGA logic cells. Most modern FPGAs use 4-input or 6-input lookup tables — physically a small MUX with programmable data inputs.

Sensor input switching. Microcontrollers route one of several analog/digital sensor inputs through an internal MUX to a single ADC channel.

Display driver column selection. Multiplexed LED matrices use a fast MUX cycling through column data while a counter cycles row addresses.

Preguntas frecuentes

Why does a 4-to-1 MUX need 2 select bits?

Because log₂(4) = 2. The select code addresses one of 4 inputs, so it needs 2 bits. In general, N-to-1 MUXes need ⌈log₂N⌉ select bits.

Can I build a 4-to-1 from three 2-to-1 MUXes?

Yes. Two 2-to-1 MUXes pair up the 4 data inputs (D0/D1 and D2/D3), each using S0 as their select. A third 2-to-1 MUX picks between the two intermediate outputs using S1. Total: 3 MUXes.

How is this used in FPGAs?

Each FPGA logic cell contains a small MUX (typically 4 to 6 inputs) whose data inputs are programmable bits. To implement any function of 4 (or 6) input variables, store the truth-table values in the data inputs and use the input variables as select. This is why FPGAs are flexible.

What's the difference between a 4-to-1 MUX and a 2-to-4 decoder?

A MUX *selects* one input and routes it; a decoder *enables* one of N output lines based on its input code. They're often used together: a decoder produces select signals; a MUX uses them. A MUX has 4 data inputs + 2 select; a decoder has 2 inputs + 4 outputs.

Can I implement any 2-variable Boolean function with a 4-to-1 MUX?

Yes. Wire the function's two variables to S1 and S0; wire the truth-table outputs (one bit per row) to D0–D3. The MUX output reproduces the function. This is the LUT principle — implement any function as a programmable lookup.