Template: 2-Bit Binary Adder
2 Bit Adder
Lo que aprenderás
- Add two 2-bit numbers using a half-adder + full-adder cascade.
- Identify why bit 0 needs only a half-adder (no carry-in below).
- Trace the carry chain from bit 0 to bit 1 to the final overflow output.
- Read the truth table for 2-bit + 2-bit binary addition (16 input combinations).
- Recognise this circuit as the building block of all wider integer adders.
Cómo funciona
Adding two 2-bit numbers (each 0–3) gives a result 0–6 — three output bits' worth. This circuit cascades a half-adder for the low bit with a full-adder for the high bit, building the foundation of every wider arithmetic circuit.
Bit 0 (low): A half-adder takes A0 and B0. Its outputs are S0 = A0 ⊕ B0 (the sum bit) and Cout0 = A0 · B0 (the carry into bit 1). A half-adder has no carry input — there's nothing below bit 0 to carry from.
Bit 1 (high): A full-adder takes A1, B1, and the carry-in from bit 0. It produces S1 (high sum bit) and Cout1 (carry out of the whole addition). Cout1 becomes the third output bit because 2-bit + 2-bit can overflow into a third bit.
The full result is a 3-bit number: Cout1 S1 S0. For example, 11 + 11 = 110 in binary (3 + 3 = 6).
This cascade is the ripple-carry adder — every higher bit has to wait for the carry from the bit below. For 2 bits the delay is small, but for 64-bit adders ripple-carry becomes too slow, motivating carry-lookahead and other accelerations.
Tabla de verdad
Two 2-bit inputs (A1A0 and B1B0). Output is a 3-bit sum (Cout S1 S0). Showing the boundary cases — full table has 16 rows.
| Entradas | Salida | ||||||
|---|---|---|---|---|---|---|---|
| A1 | A0 | B1 | B0 | Cout | S1 | S0 | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 + 0 = 0 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 + 1 = 2 (binary 10) |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 2 + 1 = 3 (binary 11) |
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 2 + 2 = 4 (binary 100, overflow into Cout) |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 3 + 1 = 4 |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 3 + 3 = 6 (binary 110) |
Expresión booleana
Low sum bit — XOR of the two LSBs.
Carry from bit 0 — AND of the two LSBs (half-adder carry).
High sum bit — XOR of A1, B1, and carry-in (full-adder sum).
Final carry — full-adder carry-out: a carry happens if both A1 and B1 are 1, OR if the carry-in propagates through (A1 XOR B1) = 1.
Pruébalo paso a paso
Configura las entradas en la simulación de arriba, lee qué debería suceder y verifícalo.
- 1A1 = 0 A0 = 0 B1 = 0 B0 = 0Esperado:
Cout S1 S0 = 000Lo que verás: 0 + 0 = 0. Default state — no carry, no sum. - 2A1 = 0 A0 = 1 B1 = 0 B0 = 1Esperado:
Cout S1 S0 = 010Lo que verás: 1 + 1 = 2. The half-adder for bit 0 produces S0=0 with carry=1 into bit 1, making S1=1. - 3A1 = 1 A0 = 0 B1 = 1 B0 = 0Esperado:
Cout S1 S0 = 100Lo que verás: 2 + 2 = 4. No carry from bit 0; bit 1 carries because both A1 and B1 are 1. - 4A1 = 1 A0 = 1 B1 = 1 B0 = 1Esperado:
Cout S1 S0 = 110Lo que verás: 3 + 3 = 6 (max input → max output). The carry chain ripples all the way to Cout.
Componentes utilizados
Aplicaciones en el mundo real
CPU arithmetic. Every CPU's integer ALU has an adder at its core. Wider adders (32-bit, 64-bit) use the same chained-full-adder pattern, often with carry-lookahead acceleration.
Address calculation. Memory address generation involves adding offsets to base addresses — typically wide adders chained from full-adder cells.
DSP filters. Digital signal processors compute sums of products; multipliers internally use rows of adders to accumulate partial products.
Counters and timers. Many counters are implemented as adders that add 1 to the current count each clock cycle.
Floating-point arithmetic. The mantissa of an IEEE 754 float is added by an integer adder after exponent alignment — the same ripple-carry-or-faster pattern.