Intel 4004-Inspired CPU: A Transparent 4-Bit Teaching Model

TL;DR: This is a working 4-bit teaching CPU inspired by the Intel 4004, not an emulator or transistor-level reconstruction. It uses a custom instruction set, unified memory, a zero flag, and a HALT operation to make fetch–decode–execute visible. The historical 4004 used a different memory organization, 46 instructions, sixteen 4-bit index registers, a three-level address stack, and a multiplexed bus. Open the template to study the teaching model, then use the source links below for the real processor.

On November 15, 1971, Intel announced the 4004, a general-purpose programmable microprocessor developed from a calculator-chip project for Busicom. Intel’s historical timeline records about 2,300 transistors and identifies the Busicom 141-PF as its first application. An Intel museum brochure lists the initial clock speed as 108 kHz; later 4004 variants and references are often associated with higher maximum rates, which is why unsourced articles disagree.

The important shift was architectural and economic: one programmable CPU design could serve multiple products when paired with memory and I/O chips, instead of replacing the CPU logic for each application. This teaching circuit makes that stored-program idea tangible, while keeping its historical distance explicit.

Can you actually build a CPU out of logic gates?

A faithful 4004 requires substantially more than a generic 4-bit datapath. The real processor multiplexes transfers over a four-bit bus, has sixteen 4-bit index registers and a three-level 12-bit address stack, and implements 46 instructions with multi-cycle timing.

The more general stored-program concepts are very buildable:

• a 4-bit datapath (the 4004’s defining trait),
• an accumulator and a flags register,
• a program counter walking through instructions held in memory,
• an instruction register and a control unit that turns each opcode into the right sequence of control signals,
• and buses that move data between all of it without colliding.

That is what this circuit is: a complete minimal 4-bit processor assembled from DigiSim components, with enough instrumentation to see its state change.

Historical 4004 versus this model

The shared 4-bit width makes the 4004 an appropriate inspiration. The remaining differences are architectural, not cosmetic, so the template should not be used to validate 4004 machine code, timing, or peripheral behavior.

Try it

Prefer the full editor? Open the Intel 4004-inspired template. The template’s existing library label uses “Intel 4004”; interpret that as inspiration, not cycle accuracy.

What happens when you press play

The control unit drives every instruction through four states — FETCH → DECODE → EXECUTE → STORE — and you can watch them on the little state lights:

1. Fetch. The program counter puts an address on the bus; RAM returns the instruction byte; the instruction register latches it.
2. Decode. The opcode’s low nibble feeds the control unit; the program counter steps to the next instruction.
3. Execute / Store. The control unit raises the right signals — read an operand from memory, route the accumulator into the ALU, perform an add or subtract, write the result back, update the zero flag.

To keep the teaching diagram legible, the machine uses three separate buses—one for addresses, one for memory operands, and one for ALU results. Its control logic must ensure that shared tri-state wires have at most one active driver. This is a pedagogical organization rather than a reproduction of the 4004’s pin-level bus protocol.

The program: 4 × 3 by repeated addition

The historical 4004 had no multiply instruction, and neither does this teaching ISA. The sample therefore uses repeated addition. This is an illustrative program; it is not recovered Busicom firmware or Intel 4004 machine code.

        ; product = 0, counter = 3, addend = 4
loop:   ACC = product + 4      ; add the multiplicand
        product = ACC
        ACC = counter - 1      ; count down
        counter = ACC
        if counter != 0 goto loop   ; the zero flag decides
        ACC = product          ; 12, for the display
        HALT

Three trips through the loop produce 12. Here, a custom zero flag controls the conditional jump. Branches in real processors also depend on conditions derived from datapath state, but the historical 4004’s condition mechanism and encoding differ from this model.

One honest detail: the display

Here’s a subtlety we hit while building it, because it’s a great lesson in its own right. This machine has a single accumulator, and it has to time-share it between the running product and the loop counter. So if you wire a display straight to the accumulator, it flickers through 0, 4, 0, 3, 2, 0, 4, 8, … — correct, but unreadable.

The model adds a dedicated product display register that latches the accumulator only when the product is written back. The two write targets differ by one address bit, so a small decode generates the enable. This register is instrumentation for the lesson, not a claimed feature of the 4004 architecture. It deliberately trades historical fidelity for a readable 0 → 4 → 8 → 12 trace.

How to review the circuit professionally

Do more than press Play:

1. Single-step one instruction. Record PC, instruction register, accumulator, zero flag, address bus, and control state before each edge.
2. Check ownership. At every state, identify the sole source allowed to drive each shared bus.
3. Trace the branch twice. Observe one loop iteration where the counter is nonzero and the final iteration where the zero condition changes control flow.
4. Change one operand. Predict the number of iterations and final result before editing memory, then verify both.
5. Separate architectural from display state. Confirm that removing the product display register changes observability, not the program’s result in memory.

That procedure turns the template from a visual demo into a falsifiable model: every claimed state transition has a value you can predict and check.

A tribute, not a forgery

This is a teaching reconstruction, not a cycle-accurate emulator or transistor-faithful 4004. It is a von Neumann-style simplification with unified memory, where the MCS-4 system separated program ROM from data RAM and used a multiplexed interface. It faithfully demonstrates generic 4-bit datapath and stored-program concepts, not the complete 4004 architecture.

That’s the whole point of a simulator. The 4004 launched a revolution from behind a sealed gold package almost nobody ever saw inside. Here, the package is open. Press play, single-step the clock, change the constants in memory, and watch a microprocessor think — one nibble at a time.

Open the Intel 4004 in DigiSim →

Primary and archival sources

• Intel’s 4004 history timeline covers the November 1971 announcement, Busicom origin, four-chip set, and 2,300-transistor count.
• Intel’s Transistors to Transformations brochure lists the initial 108 kHz clock and 10-micron manufacturing technology.
• Intel’s archived MCS-4 Assembly Language Programming Manual documents the 46 instructions, sixteen index registers, memory addressing, and three-level stack.