D Latch from Relays: Controlled Memory That Captures a Bit on Command

The previous post ended with something genuinely new in this series: a circuit that could remember. The R-S latch, built from two cross-coupled gates, held its output even after the input that set it was removed. For the first time, we had a circuit with history — one whose state depended not just on what the inputs are, but on what they were.

The S-R latch exposes two command inputs rather than one data value. For an active-high NOR latch, asserting Set and Reset together forces both outputs low, violating their intended complementary relationship. If the inputs are then released together, internal delay differences determine which state wins and the latch may pass through metastability. (An active-low NAND latch has the analogous invalid condition when both inputs are low.)

The gated D latch gives the circuit a more convenient external contract: one data input and one level-sensitive enable. Its input logic prevents software or upstream logic from intentionally requesting Set and Reset together in the steady-state Boolean model.

One input, one control line — the two-part fix

For the active-high S-R core used here, a NOT gate forms complementary data terms. With the enable applied, the intended equations are:

When $E=1$ and the circuit has settled, $D=1$ requests Set while $D=0$ requests Reset. When $E=0$, both commands are inactive and the latch holds.

This removes the invalid S-R combination from the external functional interface, but “physically impossible” would be too strong. The direct and inverted data paths have different propagation delays. If D changes while E is high, a gate-level implementation can briefly produce an unintended overlap or gap. A robust cell topology and timing constraints keep such transients from corrupting state.

The Enable input determines when the latch is transparent:

• With Enable = 0, both S and R are inactive. Changing D does not intentionally change Q, so the feedback core holds its previous state.
• With Enable = 1, Q follows D after the cell’s propagation delay.
• When Enable returns to 0, the data path closes and the last valid value is retained.

As Enable falls, the latch stops tracking D and retains the last valid value. D must be stable for the required setup and hold intervals around the closing event. A D latch is still level-sensitive: while Enable is active, input changes can propagate through it. This differs from an edge-triggered D flip-flop, which defines a much narrower sampling event.

From one latch to a register

A single D latch stores one bit. The idea scales immediately.

Place eight latches side by side and drive them with a common Enable. Present an 8-bit word, allow the latches to become transparent, keep the data stable around the closing event, and deassert Enable. The bank now retains an 8-bit word.

“Simultaneously” is an abstraction. Enable reaches different cells with some skew, every data bit has its own arrival time, and each latch has setup, hold, and propagation requirements. A design must ensure that all eight cells capture the intended word despite those differences.

Relay calculators and computers used several storage and sequencing mechanisms, including relay holding circuits, electromechanical counters, and other machine-specific arrangements. It would be inaccurate to claim that every relay computer implemented this exact gated D-latch schematic. What carries across technologies is the architectural requirement: retain state and control when new state replaces it.

Modern multi-bit registers may use edge-triggered flip-flops, latch pairs driven by non-overlapping phases, or custom storage cells. Register files are often implemented as specialized arrays rather than rows of textbook D-latch symbols.

This distinction matters when latches are cascaded. If two same-polarity latches share an active enable, data can “race through” more than one stage while the gate is open. Two-phase latch systems or master–slave/edge-triggered structures prevent that unintended transparency.

The state table in physical clothing

Because the D latch is sequential — its output depends on its history, not just its current inputs — we describe it with a state table rather than a simple truth table:

The X in the first row is a don’t-care: when Enable is low, D is irrelevant. The AND gates have cut the data path; whatever D is doing has no effect on Q. Three rows define the complete behavior of a single-bit controlled memory cell.

Compare this with the external table of the S-R latch from Post 16. There is no command row asking the D latch to set and reset at the same time. That is a functional-interface guarantee; implementation timing still needs analysis.

Try it yourself

Below is an interactive model of a relay D latch: Enable and Data drive gating logic around a cross-coupled storage core.

Work through these three experiments in order:

1. Open the gate and write. Set Enable=1, then toggle D. Q should follow after the model’s propagation delay. The latch is transparent; “follows” does not mean zero delay.

2. Close the gate and verify hold. With Enable still 1, set D=1 and wait for Q=1. Pull Enable to 0, then toggle D. Q should retain 1.

3. Test the closing boundary. Write 0, close Enable, and confirm hold. Then repeat while changing D very close to the Enable transition. A simplified model may choose a deterministic result; hardware specifications define a setup/hold aperture in which the captured value is not guaranteed.

Why the gate matters — from one cell to a computer

The cross-coupled core holds the state; Enable controls whether new data can alter it. Separating those two responsibilities gives a system a useful contract: prepare data, satisfy timing, authorize capture, and then retain the result.

At a higher architectural level, register files and memories also combine write data, an address, and a write authorization. Their internal circuitry may differ substantially from this latch, but the concepts of stored state and controlled update remain.

The R-S latch introduced persistence; the D latch makes that persistence easier to place in a datapath. It does not eliminate analog concerns. Metastability, delay, skew, contact bounce, and power-up state still belong to the implementation.

What you just built — and what’s next

Post 17 adds these to your relay toolkit:

• The D latch wraps an active-high S-R core with $S=D\cdot E$ and $R=\overline{D}\cdot E$.
• When Enable = 1, Q follows D after propagation delay. When Enable = 0, Q holds its previous value.
• The external state table excludes an intentional Set-and-Reset command, while physical timing can still create hazards.
• A bank of D latches can retain a word if data, enable skew, setup, and hold requirements are satisfied.
• Edge-triggered flip-flops, two-phase latch systems, and custom memory arrays build on the same state-update problem but are not interchangeable implementations.

This is Post 17 of Building a Computer from Relays. We now have arithmetic, a timing source, and controlled storage. In the series finale, we combine those abstractions into a small memory path while keeping the distinction between an educational construction and a complete stored-program computer clear.

DigiSim Relay Lab