The previous post ended with something genuinely new in this series: a circuit that could remember. The R-S latch, built from two cross-coupled gates, held its output even after the input that set it was removed. For the first time, we had a circuit with history — one whose state depended not just on what the inputs are, but on what they were.
But the R-S latch came with rough edges. It demanded two separate inputs — Set and Reset — when the intuition behind memory says there should be one: the value you want to store. Managing a two-handed write operation is a small but real annoyance in practice. More seriously, it carried a forbidden state. Drive Set=1 and Reset=1 at the same time and the two cross-coupled gates make contradictory demands; release them in an unpredictable order and Q can land anywhere. For a single latch in a lab, the forbidden state is something to document and avoid. For a row of latches holding a number in a running machine, it is a failure mode — one timing glitch, one voltage overlap, and a stored value can be silently corrupted.
The D latch resolves both problems in a single, elegant move. It is the R-S latch with just enough logic wrapped around it to make it clean enough to use.
One input, one control line — the two-part fix
The forbidden state is Set=Reset=1. The cleanest way to make that structurally impossible is to guarantee that Set and Reset are always opposites. If one is always the inversion of the other, they cannot both be 1 simultaneously.
A NOT gate does exactly that. Take a single input — call it D, for Data — and route it to the Set pin of the latch directly, and to the Reset pin through an inverter. Now Set=D and Reset=NOT D. When D is 1, Set goes high and Reset goes low: the latch stores a 1. When D is 0, Set goes low and Reset goes high: the latch stores a 0. Set and Reset are always opposites because one is always the complement of the other. The forbidden state is not a rule to follow — it is a physical impossibility encoded in the wiring.
That resolves the first flaw. The second requires one more piece.
In the raw form just described, the latch never stops listening. The moment D changes, Q changes. There is no way to say: hold your current value while I prepare the next one. Practical memory needs a write gate — a control signal that determines when the latch accepts its input, independently of what that input is.
That control signal is the Enable input.
Place an AND gate in each path between the data source and the latch:
- Set input to latch = D AND Enable
- Reset input to latch = (NOT D) AND Enable
When Enable = 0: both AND gates output 0 regardless of D. The latch receives Set=0 and Reset=0 — neither a store-1 command nor a store-0 command. A cross-coupled latch with both inputs low holds its current state unchanged. Q is frozen. D can wander freely; the latch will not respond.
When Enable = 1: the AND gates pass the data through. Set becomes D; Reset becomes NOT D. Q now follows D wherever it goes: raise D and Q rises; lower D and Q falls. The latch is transparent — a window, open to the data input.
Lower Enable back to 0: the AND gates cut the path. Whatever Q was at that instant is captured and held. The window closes.
That transition — Enable falling from 1 to 0 — is the moment of writing. It is the moment you choose to commit a value to memory.
Writing on command: relay registers
A single D latch stores one bit. The idea scales immediately.
Place eight D latches side by side with their Enable lines wired together. Present an 8-bit value on the eight data inputs, assert Enable high, then pull Enable low. All eight bits are captured simultaneously. You have just written a number to memory — an 8-bit register.
This is not a theoretical extrapolation. The relay computers of the 1940s were built on exactly this pattern.
The Harvard Mark I, completed in 1944 under Howard Aiken in collaboration with IBM engineers, contained 72 electromechanical accumulators, each holding a 23-digit decimal number. Its working storage was organized as relay register banks: rows of latching elements controlled by shared write-enable signals. To record an intermediate result, the control logic held the data lines stable and pulsed the write signal; the registers latched and held the value through subsequent computation steps. The Enable line — or its relay-era equivalent — was the circuit’s way of saying: this value is ready; commit it now.
George Stibitz and his colleagues at Bell Telephone Laboratories, whose Model K relay adder from Post 14 grew into the Complex Number Calculator, designed explicit register storage into their later relay machines. The logic was consistent across every Bell Labs relay machine they built through the late 1940s: a data bus carried values, a write-enable signal determined when those values landed in storage, and the register held the result until the next write command. A relay computer is not a machine that computes and forgets; it is a machine that computes and selectively remembers.
Charles Petzold makes the underlying point precise in CODE: the step from combinational logic to latches is the step from circuits that respond only to their current inputs, to circuits that carry forward a record of what they were told to remember. The Enable line is the mechanism that makes that “telling” deliberate rather than continuous.
In unbroken logical descent, that Enable line is the ancestor of every clock edge, write-enable signal, register-file write port, and load instruction in every digital system built since. The relay is gone; the function is not.
The state table in physical clothing
Because the D latch is sequential — its output depends on its history, not just its current inputs — we describe it with a state table rather than a simple truth table:
| Enable | D | Q (next) |
|---|---|---|
| 0 | X | Q (holds) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The X in the first row is a don’t-care: when Enable is low, D is irrelevant. The AND gates have cut the data path; whatever D is doing has no effect on Q. Three rows define the complete behavior of a single-bit controlled memory cell.
Compare this to the R-S latch’s table from Post 16. Where the R-S latch required an asterisk and a warning on the Set=Reset=1 row, this table has no such row. The NOT gate doesn’t just make the forbidden state unlikely — it makes the combination impossible. Every entry in the table is valid.
Try it yourself
Below is a live D latch — Enable input, NOT gate, two AND gates, and cross-coupled latch core all wired together — running as a genuine relay simulation in your browser. Not an animation: the relay contacts are switching real simulated current, and Q updates in real time as you change the inputs.
Work through these three experiments in order:
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Open the gate and write. Set Enable=1. Now toggle D back and forth. Watch Q follow D in real time — the latch is transparent, tracking its input exactly. This is the “open” state. The AND gates are passing D and NOT D straight through to the latch core, and Q responds immediately to every change. Turn your sound on: you’ll hear both AND gate contacts and the latch relay switching with each toggle.
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Close the gate and prove the freeze. With Enable still 1, set D=1 so that Q=1. Now pull Enable to 0. Toggle D: change it to 0, back to 1, to 0 again. Watch Q — it does not move. The AND gates have cut both paths to the latch core. Q holds the value it carried when Enable fell. That indifference to D is not coincidental; it is the entire point of the circuit.
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Write a 0, then re-open. Set Enable=1, set D=0 so Q falls to 0, then pull Enable back to 0. Q should now read 0 and hold it through any change in D. When you’re satisfied it’s holding, set Enable=1 again, raise D to 1, and lower Enable once more. Q is now 1. You have overwritten the stored value on command — written 0, then written 1, both times by controlling Enable, not by doing anything exotic to D.
Why the gate matters — from one cell to a computer
There is a subtlety worth sitting with. The D latch doesn’t hold a value because the value has nowhere else to go. It holds because Enable was pulled low — actively, deliberately, by the control logic that knows the value is ready. Memory is not passive storage; it is active commitment. The Enable line is the circuit’s act of decision.
That distinction becomes structural as circuits scale. A register file in a modern processor contains dozens of multi-bit registers. Each one gets written when the control logic asserts a write-enable, the data bus carries the value, and the write-enable is then deasserted. The mechanism is D latch rows with shared Enable lines, dressed in faster technology and multiplied in count. The abstraction layer is thick; the logic underneath is this table.
This is also the moment the series turns a corner. Every circuit from Post 1 through Post 16 computed a result from its current inputs and produced an output that vanished the moment the inputs changed. The D latch, like the R-S latch before it, produces a state that persists — a result that survives the removal of the inputs that created it. Feedback gives a circuit memory. That property, now tamed and controlled through the Enable line, is what every register, counter, processor, and stored-program computer is built on.
What you just built — and what’s next
Post 17 adds these to your relay toolkit:
- The D latch wraps an R-S latch with a NOT gate and two AND gates. Set = D AND Enable; Reset = (NOT D) AND Enable. The NOT gate eliminates the forbidden state. The AND gates add the write gate.
- When Enable = 1, Q follows D — the latch is transparent. When Enable = 0, Q holds its last value regardless of what D does.
- The state table has three rows and no forbidden state — the cleanest description of single-bit controlled memory.
- Eight D latches sharing one Enable line form a register — the unit of working memory in every relay computer, every chip, and every microprocessor ever built.
- The Enable line is the direct ancestor of every write-enable, clock edge, and load signal in sequential digital logic.
This is Post 17 of Building a Computer from Relays. We now have arithmetic (the full adder from Post 14), timing (the clock), and storage (this D latch). In the series finale, we close the loop: a clean 1-bit memory cell — the kind a programmer can write to and read from on command — and a view of how rows of such cells, joined to the adder and the clock, constitute a stored-program computer in the most literal sense. The relay lab will be open, and every part will be a circuit you have already met.