1-Bit Relay Memory: A Storage Building Block — and the Series Finale

In the previous post, we built a D latch: a level-sensitive circuit with a Data input and a Write-enable line. While Write is asserted, the latch is transparent and Q follows Data after the modeled delay; when Write is deasserted, feedback retains the last value. That behavior gives us a useful one-bit storage abstraction. One packaging step remains before we can treat it as a reusable block.

This is Post 18 of Building a Computer from Relays — the last stop. We are going to finish that memory cell, name it for what it is, and then do something this series has been building toward for seventeen posts: trace every rung of the ladder we have climbed, together, all the way from a single clicking switch to the stored bit.

The result is not the physical cell used by every kind of RAM. It is a teaching model for the state, write-control, and readout behavior that larger memories must provide.

Packaging the 1-bit memory cell

The D latch already provides the state-holding behavior. It has a Write-enable line (often called EN or WE) and a Data line (D), and it retains the final value presented while Write was high. As a raw circuit, however, it exposes its relay feedback and internal nodes. Packaging it behind a small interface lets the surrounding design depend on behavior rather than topology.

A 1-bit memory cell is the D latch, packaged with a clean interface contract:

• Write — a single control line. Assert it high (1) to write; hold it low (0) to read or just hold.
• Data — the bit you want to store: 0 or 1.
• Q — the stored output. Reflects Data while Write is 1; holds its last value when Write drops back to 0.

Everything else — including the feedback and the gating that derives valid internal drive conditions — is encapsulated. The state table for this level-sensitive cell is small:

That dash in the Data column when Write is 0 is the whole point. When Write is low, Data is irrelevant. The cell is not listening. It holds what it last heard — and it will keep holding it for as long as power is supplied.

Notice what the state table cannot say: it cannot tell you what Q is now without an initial condition or the value written previously. Memory has state. It is not a pure function of current inputs; it depends on input history. That is the defining distinction between combinational logic and sequential storage. A real implementation also needs power-up, reset, timing, loading, and invalid-condition behavior that this three-column table does not specify.

Scaling up: from one bit to one computer

Here is where the abstraction earns its weight.

Eight independently stored bits form one byte, which can represent an unsigned value from 0 to 255. Turning cells into an addressable memory also requires word lines, bit lines, address decoding, read/write circuitry, sensing, timing, and often refresh or error-control logic. Decimal prefixes use 1 kB = 1,000 bytes, while binary prefixes use 1 KiB = 1,024 bytes; the distinction grows at MB/MiB and GB/GiB scales.

The same abstract question—what value is stored, and under what condition may it change—applies across technologies, but the physical cells are not scaled D latches. Static RAM (SRAM) commonly uses a cross-coupled transistor cell with access devices; dynamic RAM (DRAM) stores charge and requires sensing and refresh; nonvolatile memories use still other mechanisms. Their interfaces can expose similar logical behavior while their device physics, density, timing, endurance, and power-loss behavior differ substantially.

Try it yourself

Below is the memory-bit cell, a D latch packaged as a one-bit block in the browser-based Relay Lab. It is an interactive simulation, not physical hardware: the model updates relay/contact state and circuit values according to the simulator’s rules, and Q retains simulated state.

Work through this sequence deliberately:

1. Store a 1. Set Data = 1, then assert Write = 1. The cell latches; Q goes to 1. Now release Write back to 0. Data doesn’t matter anymore — wiggle it, flip it to 0, disconnect it in your imagination. Q stays at 1. You just stored a bit.

2. Overwrite with a 0. Set Data = 0, then pulse Write high again briefly. Q falls to 0. Release Write. Q holds 0. You just overwrote the bit.

3. Confirm it holds under silence. Leave both Write and Data at 0. Q remains 0. The cell is not reacting to inputs; it is simply remembering the last thing you told it.

You have exercised one bit of modeled state. An array of such abstractions, combined with selection and read/write circuitry, is a useful first model of random-access memory. Do not infer a commercial RAM cell topology from the relay implementation.

The ladder you climbed

This series had a plan from the first click of Post 1. Before we look at the relay computers that ran on circuits like these, let’s retrace every rung together — because seen all at once, the arc is remarkable.

Post 1 — The relay itself. A switch that electricity controls. A coil pulls an armature; the armature moves a contact; one circuit throws a switch in another circuit. Wired normally-open it’s a buffer; wired normally-closed it’s an inverter. That click was not just a pleasant sound. It was the seed of everything.

Posts 2–3 — Series and parallel. Two switches in series, and current only flows when both are closed: AND. Two switches in parallel, and current flows when either closes: OR. No gate symbols yet — just wire and the observable behavior of current. Logic was already there, written in copper.

Posts 4–7 — The named gates. AND, OR, and NOT got names and symbols, courtesy of George Boole’s algebra and Claude Shannon’s 1937 proof that relay networks and Boolean algebra are the same thing. The buffer, the inverter, the gate trio — all first-principles builds in relay hardware.

Posts 8–9 — The universal gates. NAND and NOR: each one capable of implementing any logic function in existence. The simplicity is disorienting — one gate type, wired creatively, yields all the others. Followed by the Apollo Guidance Computer’s famous dependence on NOR gates: the Moon mission flew on a circuit you could now build yourself.

Posts 10–11 — XOR and XNOR. The difference detector. XOR produces 1 when its inputs disagree — a surprisingly powerful idea that shows up in error detection, encryption, and, crucially, arithmetic.

Posts 12–13 — The adder. XOR produces a half adder’s sum bit; AND produces its carry. Adding a carry-in gives a full adder, and chaining full adders gives a ripple-carry adder. Ripple carry remains important for instruction and for some implementation points, but high-performance arithmetic may use carry-lookahead, prefix, carry-select, FPGA carry-chain, or hybrid structures. George Stibitz’s 1937 relay experiments are an important early example of binary arithmetic implemented with electromechanical switching.

Posts 14–16 — Feedback and the clock. Feedback can create oscillation; a deliberately designed oscillator can provide a periodic clock. In a synchronous teaching computer, clock edges coordinate state updates. Clocks are not the only possible sequencing method—asynchronous circuits use handshakes and local timing—but they make state transitions easier to organize and observe in this series.

Post 17 — The D latch. Feedback turned constructive: cross-coupled relays that hold a state until instructed to change it. The Write-enable line that prevents the forbidden (both-relays-on) state. Controlled memory in a relay circuit.

Post 18 — The 1-bit memory cell. Package the D latch behind a clean interface. Write high to store; Write low to hold. Stack eight for a byte. Stack millions for a megabyte.

And now the payoff.

A computer is, at bottom, four things:

1. A clock — a regular oscillator that beats time and tells every other circuit when to act.
2. An ALU — an arithmetic and logic unit: adders, comparators, boolean operations.
3. Memory — storage that retains state between operations; volatile memory normally loses that state when power is removed.
4. Control and selection — multiplexers, decoders, and instruction logic that route the right data to the right place at the right time.

The series has introduced simplified relay examples of these functions. A complete computer still needs a defined instruction set and data path, sequencing, addressing, input/output, initialization, fault behavior, and extensive verification. Scale and organization are therefore design problems in their own right, not merely a request for more wire.

Documented relay-computer milestones

Relay and electromechanical computers of the 1940s used related switching and state ideas, but their decimal/binary representations, storage mechanisms, sequencing, and arithmetic architectures were more varied than this teaching cell suggests.

Konrad Zuse’s Z3 was completed in 1941. The Computer History Museum describes it as an early binary computer using about 2,300 relays, a 22-bit floating-point word, and punched-film program input; it was destroyed in a 1943 air raid. The museum separately calls it the first program-controlled electromechanical digital computer. Such labels depend on carefully stated criteria: the Z3 read a fixed instruction sequence from external film and did not implement a modern stored-program architecture.

In the United States, Howard Aiken and IBM developed the Harvard Mark I, formally the IBM Automatic Sequence Controlled Calculator, which entered service at Harvard in 1944. The IEEE milestone record describes a 51-foot electromechanical machine with decimal counters, switches, control circuits, and approximately 3,500 multipole relays. Instructions arrived on punched tape, and multiplication took seconds rather than microseconds. This was not simply a room-sized version of the binary D-latch array above.

The Mark I was followed by the Mark II in 1947 — a similar electromechanical machine, also at Harvard. And it is the Mark II that gave us one of computing’s most enduring stories.

In September 1947, Mark II operators found a moth in the machine and taped it into their logbook with the note “First actual case of bug being found.” Grace Hopper worked with the Mark II team, but the surviving record does not justify attributing the discovery to her alone. The Smithsonian object record also notes that the word “bug” for a technical fault predates this event.

The logbook page and moth survive in the Smithsonian’s National Museum of American History collection; the catalog currently says the object is not on display.

The incident is memorable because it made an existing engineering term literal. It should be presented as an episode that helped popularize “bug” and “debug,” not as the origin of either word.

The lineage: relay → vacuum tube → transistor → chip

Relay computers coexisted with, and were increasingly displaced by, faster vacuum-tube electronic computers. A tube can use a control grid to influence electron flow without a mechanical armature, but substituting tubes was not merely a device swap: voltage levels, amplification, fan-out, power, cooling, reliability, timing, and circuit topology all changed. Equivalent Boolean functions could be implemented in a different physical design.

Transistors then became the dominant switching devices. A bipolar junction transistor has base, collector, and emitter terminals; the MOSFETs prevalent in modern digital CMOS instead use gate, source, drain, and body terminals. Transistor logic removed mechanical contacts and heater filaments, but again required new logic families, fabrication methods, signal margins, and architectures.

From the late 1950s onward, integrated-circuit techniques placed multiple electronic components on one substrate; successive process and design advances later made systems with billions of transistors practical. Boolean algebra still describes the intended two-valued logic, while device physics, interconnect, memory hierarchy, parallelism, and microarchitecture determine how a modern chip realizes that behavior.

The relay in Post 1 and a CMOS transistor can both participate in controlled switching networks. That functional analogy is valuable, but it does not establish equal switching behavior, circuit topology, clock rate, or computer architecture. Shannon’s switching-algebra result explains why relay contact networks can be analyzed with Boolean algebra; the same algebra also supports digital CMOS design at a higher abstraction level.

The relay is therefore one instructive path into digital logic history—not a complete lineage for all computing technologies.

Where to go from here

Three honest recommendations for the reader who has made it to the end of this series.

First: build something bigger. The circuits in this series were sized for a blog post. Chain full adders, add a register and clock, and verify the resulting state sequence. The DigiSim Relay Lab includes larger teaching circuits such as an adding machine, counter, flip-flop, and frequency divider. Treat the displayed clicks and electrical behavior as outputs of the simulation model, then compare the model with component timing and contact behavior in physical data sheets.

Second: read Charles Petzold’s CODE. This series was deeply inspired by it. Petzold’s book starts with Morse code and flashlights and ends at a working CPU, built step by step from first principles in a way that is simultaneously rigorous and humane. He covers the same ground we have covered here — and then he keeps going, into machine language, assembly, operating systems. If you want a book that does for reading what DigiSim does for simulation, CODE is it.

Third: build your own. Open the DigiSim canvas, drop a relay, and wire something that came to you while reading this series. The jump from “following someone else’s circuit” to “designing my own” is the real graduation. It does not require any new knowledge. You have everything you need. Go make the relays click on your terms.

Seventeen posts ago, you met an electrically controlled switch. The final exercise packages relay feedback into a reusable storage abstraction and shows both the value and the limits of carrying that abstraction into later technologies.

Go watch a computer made of relays actually run: DigiSim Relay Lab.