In the previous post, we saw what happens when feedback chases itself around a loop with no place to land: the output flips, which triggers a flip back, which triggers another flip forward — an oscillation that never settles, producing the ticking heartbeat of a clock signal. Feedback made the circuit restless.
Now we are going to take that same ingredient — an output wired back to influence its own input — and aim it at exactly the opposite goal. Instead of a circuit that cannot rest, we will build one that settles into a stable state and stays there, even after the signal that drove it into that state has been removed.
That property has a name: memory. A circuit whose output depends not only on what its inputs are right now but on what they were in the past. Every combinational circuit in this series — the AND gate, the adder, the multiplexer — forgets the moment its inputs change. The RS latch does not. It is the first circuit in this series that remembers, and it is the direct ancestor of every bit of RAM in every computer ever built.
Same ingredient, opposite result. Here is how it works.
Two gates, two stable states: the cross-coupled loop
Start with a single relay gate that inverts — a NOR gate, which outputs 1 only when neither of its inputs is 1. Now imagine two of them, wired in a loop: the output of Gate A feeds one input of Gate B, and the output of Gate B feeds one input of Gate A. Each gate’s output is the other gate’s input. This arrangement is called cross-coupling.
Follow the logic around. Suppose Gate A’s output is 1. Gate B sees a 1 on its input from A and computes NOR(1, …) = 0. Gate B’s output is 0. That 0 feeds back into Gate A. Gate A now computes NOR(0, …) = 1 — right back where we started. The loop is stable. Call this the first resting state.
Now suppose Gate A’s output is 0. Gate B sees 0 from A and computes NOR(0, …) = 1. That 1 feeds back to Gate A. Gate A computes NOR(1, …) = 0. Also stable. A second resting state, the mirror image of the first.
Two inputs, two stable configurations, zero ambiguity. The circuit will happily sit in whichever state it finds itself in. This is bistability — the condition that makes memory possible. The key difference from the oscillator: the oscillator had an odd number of inversions, creating an impossible contradiction that forced perpetual motion. The cross-coupled pair has an even number, and both ways around the loop are self-consistent. The circuit finds peace in either position.
The RS latch adds one refinement: instead of plain inverters, each gate has a second input — a handle you can grab to force the circuit from one state to the other. Set input S on one gate, Reset input R on the other. Pull S high and the feedback loop snaps into the Set position. Pull R high and it snaps into the Reset position. Release the input, and the feedback loop takes over and holds the new state on its own.
In a relay implementation, each NOR gate is a relay whose coil is energized by either of two inputs in parallel — a relay that pulls in, and opens its normally-closed contact, when either the control signal or the feedback from the other gate is active. Two such relays, cross-coupled, click once when SET and again only when RESET. Between those clicks, no current flows into either coil, and yet the output is held — by the geometry of the feedback, not by any ongoing input.
Eccles, Jordan, and the flip-flop that started everything
The first person to publish this bistable circuit was not working on computers. He was not even thinking about logic. William Eccles, a British physicist, and his collaborator Frank Jordan were interested in trigger circuits — ways to use a small signal to “pull a trigger” that released a much larger stored state. In 1918 and 1919 they published descriptions of what they called the “trigger relay”: a pair of cross-coupled triode vacuum tubes, each holding the other in a stable state, switchable by a brief pulse.
Their circuit behaved exactly as described above, but with vacuum tubes instead of relays. One tube conducting, the other cut off. A pulse on the right grid flips the state. The tubes settle, and stay. Remove the pulse: still settled. This was the first electronic circuit that could hold one of two stable states and store a bit of information between operations.
The name “flip-flop” entered the engineering vocabulary in Eccles and Jordan’s own subsequent papers — a vivid, physical description of a circuit that flips one way and can be flopped the other way back. It is arguably the best name in all of electronics. Every flip-flop in every processor chip today — the billions of storage cells that hold the state of your program from one clock tick to the next — descends from that 1918 vacuum-tube circuit.
Charles Petzold, in CODE: The Hidden Language of Computer Hardware and Software, calls memory the dividing line between a machine that merely calculates and a machine that can truly compute. Eccles and Jordan drew that line in hardware a century ago. The RS latch — also called the SR latch, with the inputs named in the other order — is where the bit was born.
The state table: four combinations, four outcomes
A truth table works for combinational circuits, where the output depends only on the current inputs. The RS latch is a sequential circuit: its output depends on both the current inputs and the circuit’s current state. For sequential logic, the right tool is a state table, which makes that history explicit.
The latch has two inputs — S (Set) and R (Reset) — and one primary output, Q. Here is what each combination does:
| S | R | Q (next) | Meaning |
|---|---|---|---|
| 0 | 0 | Q (holds) | Neither input asserted — the latch holds its last state |
| 0 | 1 | 0 | Reset: Q is forced to 0 and stays at 0 after R returns to 0 |
| 1 | 0 | 1 | Set: Q is forced to 1 and stays at 1 after S returns to 0 |
| 1 | 1 | invalid | Both gates forced simultaneously — outcome is ambiguous, avoid |
The first row is the remarkable one. When both S and R are 0 — when neither input is being driven at all — Q retains its previous value. The circuit is remembering without any external assistance. This is the read condition: you can inspect Q as many times as you like without changing what it holds.
The second and third rows are the write conditions. Briefly assert R and Q falls to 0; briefly assert S and Q rises to 1. Remove the input, and Q holds the new value. The latch has been written.
The fourth row demands an honest explanation. When S = 1 and R = 1 simultaneously, both NOR gates are forced: each sees a 1 on its control input and drives its output to 0. The result is Q = 0 and not-Q = 0 — both outputs low at once, violating the complementary relationship they are supposed to maintain. More dangerously, when S and R are both released at the same instant, neither gate has a dominant input. Each sees the other’s output as 0 and tries to drive its own output to 1 — but that 1 immediately forces the other gate back to 0. The circuit enters a race. Which gate wins depends on microscopic differences in relay timing and contact physics. The output may settle to Q = 0, or to Q = 1, or oscillate briefly before landing somewhere. None of those outcomes are predictable or repeatable.
This is the forbidden state, and avoiding it is the designer’s job. It is not a quirk or a flaw to be ashamed of — it is an honest consequence of forcing two gates into an impossible simultaneous demand. Every more sophisticated storage element you will meet in this series exists partly to solve this problem cleanly.
Try it yourself
Below is a relay RS latch: two cross-coupled NOR gates, wired from real relay components in a genuine DC circuit simulation — not an animation. Both S and R start at 0. The latch is holding its initial state silently, with nothing driving it.
Work through these three experiments in order:
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The holding moment — the whole point. Pulse S high, hold it a beat, then release it. Watch Q: it’s 1, and S is 0, and nothing is driving Q to stay that way — except the feedback loop inside the latch. The circuit is remembering what you told it. Sit with that for a moment before moving on. This is the bit being born. The input is gone; the state remains. This is what Eccles and Jordan built in 1918, and it is the foundation of every register, every cache line, every byte of RAM.
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Reset and re-set. Now pulse R. Watch Q drop to 0 and the latch click into its Reset state. Release R. Q stays at 0. Pulse S again: Q jumps back to 1. You have just written a 0 and then written a 1 into a one-bit memory cell. You can do this as many times as you like. Each pair of clicks is a bit being changed, held, and changed again.
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The forbidden state. Raise both S and R simultaneously. Observe: both outputs are forced to the same value, and the complementary structure collapses. Now release both at the same instant and watch what the latch does — the outcome is not guaranteed. This is not a simulation bug; it is the real physics of an ambiguous input condition. Now you understand in your hands why engineers mark S = R = 1 as a design error in every textbook from 1950 onward.
Memory is the border between calculator and computer
Every circuit in this series before today was stateless: give it the same inputs and you always get the same output, regardless of what it did a moment ago. The AND gate does not know whether it just changed from 0 to 1 or has been outputting 1 all day. The full adder from Post 14 produces a sum and a carry-out and then immediately forgets it computed anything at all.
That is fine for arithmetic — arithmetic does not need to remember. But a programmable computer does. To execute a sequence of instructions, the machine must carry results from one step to the next. To run a loop, it must track how many iterations remain. To respond differently to the same instruction depending on what happened earlier, it must hold state. A machine without memory can only respond to what is in front of it right now. A machine with memory can act on what it has experienced.
The RS latch — also known as the SR latch — is the simplest circuit that crosses that line. It stores a single bit. That bit can be written by driving S or R, read by inspecting Q, and rewritten at will. Chain eight of these together and you have a byte. Chain a few thousand bytes together with address logic and you have a memory array. The architecture of every RAM chip in history is, at its logical core, a sea of bistable feedback loops identical in principle to what you just toggled in the simulation above.
This is why Charles Petzold, Shannon’s heirs, and every digital-logic textbook spend significant time on the RS latch before moving to anything more complex. Not because it is the most useful form of memory — it has that forbidden-state problem, and later circuits fix it — but because it is the most transparent form. You can see exactly why it remembers.
What you just learned — and what’s next
This post crossed a threshold in the series:
- Feedback can settle, not just oscillate. Cross-couple two inverting gates and the loop finds two stable positions, holding whichever one it is placed in.
- The RS latch is a sequential circuit. Its output depends on history, not just present inputs — which is why it needs a state table, not a truth table.
- Set forces Q to 1 and it holds; Reset forces Q to 0 and it holds; neither input leaves Q unchanged. The hold row — S = 0, R = 0, Q stays — is the memory in action.
- S = R = 1 is the forbidden state. Both gates are forced simultaneously; the outcome when inputs are released is ambiguous by design.
- Eccles and Jordan published the first bistable circuit in 1918. Their “trigger relay,” later called the flip-flop, was the first device that could store a bit — the birth of computer memory.
In Post 17 — The D Latch, we tame the RS latch’s one glaring weakness. Instead of two separate Set and Reset lines with their dangerous interaction, a D latch takes a single Data input and a separate Enable signal. You specify what to store on D, and when to store it on Enable. The forbidden state disappears. The result is clean, controllable, one-bit memory — the cell that fills every register in every processor.
Want to explore bistable circuits and wire your own relay memory? DigiSim Relay Lab