The RS Latch: Bistable Feedback and One-Bit State

The previous post examined an inverting feedback loop. In a physical implementation with sufficient loop gain and propagation delay, an odd-inversion loop can oscillate; in a digital simulator, that behavior depends on the event and delay model. Feedback can also produce stable state rather than periodic motion.

Here, two outputs are cross-coupled so that the powered circuit has two stable operating points. A control input can select one state; after that control is deasserted, regenerative feedback retains the selected state.

That property has a name: state. Its output depends not only on current inputs but also on a previous condition. Every combinational circuit in this series—the AND gate, adder, and multiplexer—has no stored state. The RS latch is the first circuit in the series that remembers. Its cross-coupled feedback is a conceptual foundation for static storage, but not every RAM technology is an RS-latch array: DRAM, for example, stores charge on capacitors.

The following sections derive that behavior and its limits.

Two gates, two stable states: the cross-coupled loop

Start with a single relay gate that inverts — a NOR gate, which outputs 1 only when neither of its inputs is 1. Now imagine two of them, wired in a loop: the output of Gate A feeds one input of Gate B, and the output of Gate B feeds one input of Gate A. Each gate’s output is the other gate’s input. This arrangement is called cross-coupling.

Follow the logic around. Suppose Gate A’s output is 1. Gate B sees a 1 on its input from A and computes NOR(1, …) = 0. Gate B’s output is 0. That 0 feeds back into Gate A. Gate A now computes NOR(0, …) = 1 — right back where we started. The loop is stable. Call this the first resting state.

Now suppose Gate A’s output is 0. Gate B sees 0 from A and computes NOR(0, …) = 1. That 1 feeds back to Gate A. Gate A computes NOR(1, …) = 0. Also stable. A second resting state, the mirror image of the first.

The two complementary configurations are stable under the ideal Boolean model. This is bistability. It does not imply a defined power-up state: without a reset, component mismatch, noise, supply sequencing, and model event ordering can determine which state is reached. An odd-inversion physical loop may oscillate when its gain, delay, and frequency response satisfy the oscillation conditions; an even-inversion regenerative pair instead admits two self-consistent static states.

The RS latch replaces the plain inverters with gates that expose control inputs. For an active-high NOR latch, asserting S selects the Set state and asserting R selects the Reset state. After that input returns LOW, feedback maintains the state while the circuit remains powered and its electrical operating limits are satisfied.

One relay implementation can form each NOR function with a coil driven by the logical OR of its control input and the other stage’s feedback, while a normally closed contact supplies the inverted output. In a stable complementary state, one relay can remain energized and the other released; this is powered volatile storage, not a zero-energy mechanical memory. Coil voltage, driver current, contact ratings, release behavior, and contact bounce belong to the physical design even when an educational model abstracts them.

Eccles, Jordan, and the flip-flop that started everything

William Eccles and Frank Jordan developed their bistable vacuum-tube trigger before electronic digital computers. Jordan applied for the relevant British patent in June 1918, and Eccles and Jordan described the trigger relay in the December 1919 issue of The Radio Review. The circuit used cross-coupled triodes and could be switched between two stable conditions by a trigger.

In its stable conditions, one tube conducted while the other was cut off. The historical circuit is widely recognized as the first flip-flop or bistable multivibrator. Describing it as one-bit storage is a later digital interpretation: it predated modern logic-level conventions and was originally presented as a trigger circuit for radio work.

The Eccles–Jordan circuit established the regenerative bistable principle later used across many latch and flip-flop families. Contemporary storage cells differ greatly in transistor topology, clocking, density, and purpose, but the idea of two stable states maintained by feedback remains fundamental.

The RS latch—also called the SR latch—is now a standard teaching model for regenerative one-bit storage. It should not be treated as the origin of all memory technology: delay lines, magnetic cores, capacitors, floating-gate devices, and other mechanisms store information in different ways.

The state table: four combinations, four outcomes

A truth table works for combinational circuits, where the output depends only on the current inputs. The RS latch is a sequential circuit: its output depends on both the current inputs and the circuit’s current state. For sequential logic, the right tool is a state table, which makes that history explicit.

The latch has two inputs — S (Set) and R (Reset) — and one primary output, Q. Here is what each combination does:

In the first row, both active-high controls are driven LOW; they are not electrically floating. Q retains its previous valid value through powered feedback. Observing Q with a receiver that stays within the output’s load limit does not intentionally change the stored state.

The second and third rows are the write conditions. Briefly assert R and Q falls to 0; briefly assert S and Q rises to 1. Remove the input, and Q holds the new value. The latch has been written.

The fourth row demands an honest explanation. When S = 1 and R = 1 simultaneously, both NOR gates are forced: each sees a 1 on its control input and drives its output to 0. The result is Q = 0 and not-Q = 0 — both outputs low at once, violating the complementary relationship they are supposed to maintain. When S and R are then released together, neither gate has priority. Small differences in propagation delay, noise, and device behavior determine which stable state wins; a physical electronic latch can also pass through metastability and resolve later than downstream logic permits. The final state is therefore unspecified, even if a simplified simulator resolves the event deterministically.

This is conventionally called the invalid or forbidden input combination for a basic NOR latch with complementary outputs. A design must prevent it or explicitly define how assertion and release are handled. Other latch and flip-flop interfaces hide this particular command combination, but they still impose timing, initialization, and metastability requirements.

Try it yourself

Below is a DigiSim Relay Lab model of two cross-coupled NOR stages. It represents circuit behavior according to the simulator’s relay and electrical models; it is not a calibrated measurement of a specified physical relay assembly. Both control inputs start LOW, and the model resolves to an initial state according to its initialization rules.

Work through these three experiments in order:

1. The holding moment. Pulse S high, then release it. Q remains 1 because the feedback loop sustains one stable state. This demonstrates the same bistability principle that underlies many static storage circuits.

2. Reset and re-set. Now pulse R and verify that Q becomes 0. Release R, then pulse S and verify that Q becomes 1. This writes the two valid states in succession. Relay sound and transition timing are properties of the selected simulation model, not universal relay specifications.

3. The forbidden state. Raise both S and R simultaneously. Both NOR outputs are forced low, violating the expected complementary relationship. Releasing both together leaves the final physical state sensitive to tiny delay and noise differences and can produce metastability. A digital simulator may choose deterministically or show an unknown according to its model; it cannot reproduce the analog resolution distribution.

Memory is the border between calculator and computer

Every circuit in this series before today was stateless: give it the same inputs and you always get the same output, regardless of what it did a moment ago. The AND gate does not know whether it just changed from 0 to 1 or has been outputting 1 all day. The full adder from Post 14 produces a sum and a carry-out and then immediately forgets it computed anything at all.

Combinational arithmetic alone does not retain its result. A stored-program computer requires state for architectural registers, control sequencing, memory, and interfaces. Different systems realize that state with several storage technologies and organizations; the RS latch provides one transparent introduction to the feedback principle.

The RS latch—also called the SR latch—stores one bit. Placing eight independent latches side by side gives eight bits of storage, but a usable byte register also needs coordinated write control and output behavior. A memory array additionally needs word-line decoding, bit lines, read/write circuitry, sensing, and technology-specific cells. SRAM uses bistable feedback; DRAM and several nonvolatile memories store information by different physical mechanisms.

The basic RS latch is pedagogically useful because its state equations expose regenerative feedback directly. Practical storage elements add or change control, timing, readout, initialization, density, and physical implementation according to the system requirement.

What you just learned — and what’s next

This post crossed a threshold in the series:

• Feedback can settle, not just oscillate. Cross-couple two inverting gates and the loop finds two stable positions, holding whichever one it is placed in.
• The RS latch is a sequential circuit. Its output depends on history, not just present inputs — which is why it needs a state table, not a truth table.
• Set forces Q to 1 and it holds; Reset forces Q to 0 and it holds; neither input leaves Q unchanged. The hold row — S = 0, R = 0, Q stays — is the memory in action.
• S = R = 1 is the forbidden state. Both gates are forced simultaneously; the outcome when inputs are released is ambiguous by design.
• The Eccles–Jordan trigger is an early landmark in electronic bistable circuits. The patent application dates to 1918 and the widely cited journal description to 1919; its one-bit interpretation belongs to later digital engineering.

In Post 17—The D Latch, one Data input and an Enable signal derive mutually exclusive set/reset controls during normal operation. That removes the SR truth-table conflict, although real latches still have timing and metastability constraints. Registers may then be built from D latches, D flip-flops, or technology-specific storage cells.

Want to explore bistable circuits and wire your own relay memory? DigiSim Relay Lab

Historical references

• IEEE Spectrum, Re-creating the First Flip-Flop distinguishes Jordan’s June 1918 patent application from the December 1919 journal article.
• The IEEE Technology Navigator overview of bistable circuits identifies the Eccles–Jordan vacuum-tube circuit as the earliest form of the bistable multivibrator.